Altera SoC Embedded Design Suite - Manual (Page 162)

Figure 5-35: DTSL Configuration Editor - Trace Buffer > Timestamp Frequency
Cortex-A9 Settings
The Cortex-A9 tab allows the selection of the desired core tracing options.
Figure 5-36: DTSL Configuration Editor - Cortex-A9
The following Core Tracing Options are available:
• Enable Cortex-A9 0 core trace – check to enable tracing for core #0
• Enable Cortex-A9 1 core trace – check to enable tracing for core #1
• PTM Triggers halt execution – check to cause the execution to halt when tracing
• Enable PTM Timestamps – check to enable time stamping
• Enable PMT Context IDs – check to enable the context IDs to be traced
• Context ID Size – select 8-, 16- or 32-bit context IDs. Used only if Context IDs are enabled
ug-1137
2014.12.15
Cortex-A9 Settings 5-37
ARM DS-5 Altera Edition Altera Corporation
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