BECKHOFF PHY - Manual (Page 11)

EtherCAT over Optical Links (FX)
Slave Controller – Application Note PHY Selection Guide 8
5.2.1.1 Issue: Temporary Enhanced Link Detection while EEPROM is loading
Enhanced Link Detection is enabled after Reset, and it can only be disabled by EEPROM. This takes about
170 ms. In the meantime, the FX PHYs are powering up. Since they do not need to go through an auto-
negotiation sequence, the link (signal detect) comes very early. It is possible that the link is detected, but
communication is not possible (RX_ERR are detected). This can trigger the ESC to restart auto-negotiation
before the EEPROM is loaded, resulting in potential PHY problems with the restart auto-negotiation request.
The recommended solution to overcome this issue is to power up the FX PHY (and the transceiver) at least
170 ms after the ESC, e.g. by an additional reset controller with delay or power sequencing (Figure 4 or Figure
5).
Another, recommended solution is the Enhanced FX Link Detection, discussed later.
5.2.1.2 Minimum solutions with Standard Link Detection
These two solutions represent the minimum solution for proper power-up and reset operation, but they have
drawbacks in detection low quality links. The preferred solution is the Enhanced FX Link Detection, see later.
Ethernet PHY
nRESET nRESET
ESC
Reset
release
delay
>170 ms
Transceiver
MDC/MDIO
RX/TX
MDC/MDIO
V CC
Vcc
V CC
Vcc
nReset
Figure 4: PHY reset release delay with transceiver power down/reset
Ethernet PHY
nRESET nRESET
ESC
Transceiver
MDC/MDIO
RX/TX
MDC/MDIO
Power delay
>170 ms
V CC
Vcc Vcc
Vcc
nReset
Figure 5: PHY power sequencing with transceiver power down/reset
5.2.2 Enhanced FX Link Detection
In order to detect erroneous links fast enough, it is desirable to use the error detection principle of Enhanced
Link Detection also for FX PHYs. One possible solution is to use the Enhanced Link Detection logic inside the
ESC, and another possible solution is to implement enhanced link detection logic with external logic, e.g. a
CPLD.
The preferred solution is to let the ESC count the RX_ERR of the PHY, and to detect the restart auto-
negotiation request of the ESC by some additional logic (CPLD or µController etc.) attached to the MII
management interface. This logic should reset the PHY and the Transceiver (power-down) for a short time. This
reset causes a link down, which will be detected by the local ESC (which will leave its potential dead-lock state),
and by the communication partner (link down, loop closed). If this solution is chosen, Enhanced Link Detection
can be enabled in the EEPROM.
The MII management interface is still connected to the PHY, the CPLD/µC just snoops the bus. It is possible to
use one CPLD/µC for all ports of the ESC. The PHY address has to be evaluated and individual reset outputs
for each PHY have to be used.
Take care that a reset coming from the ESC also turns at least the transceiver off, in order to enable the
communication partner to close the loop.
NOTE: Some PHYs use the “signal detect” input to switch into FX operation mode. If the transceiver is powered down, the
PHY might not enter FX mode correctly. Other PHYs might not properly keep the auto-negotiation feature turned off,
especially as the ESC tries to enable it with the auto-negotiation restart command. In such a case the PHY is required to be
put into reset or power-down state, too.