BECKHOFF PHY - Manual (Page 8)

Example Ethernet PHYs
Slave Controller – Application Note PHY Selection Guide 5
4.3 Example Ethernet PHYs
Table 3: Example Ethernet PHYs assumed to fulfill EtherCAT requirements
Vendor / Device
ET1200
suitable ET1100
suitable IP Core
suitable
# Ports
Basic
HW
test
6
TX_CLK fixed
phase
7
PHY
addr.
8
PHY addr.
offset
9
Link loss
reaction time Enhanced Link
Detection Auto-TX-Shift
(IP Core only)
Comments
Broadcom
BCM5221 X X X 1
yes
(Data sheet
10 ) 0-31 0 1.3 µs recommended 11 Requires additional write clock on MDC. Quartz oscillator required. Internal pull-down at MDC.
BCM5222 X X X 2 yes (Data sheet) 0-31 0 1.3 µs recommended 11 Requires additional write clock on MDC. Quartz oscillator required. Internal pull-down at MDC.
BCM5241 X X X 1 yes yes (Data sheet) 0-7, 8,
16, 24 0 45 µs required Requires additional write clock on MDC. Quartz oscillator required. Internal pull-up at MDC. XTALI
voltage
≤ 1.8V.
Cortina Systems
LXT973 (X 12 ) (X 12 ) X 2 yes Measurement 12 0-31 0 1.9 ms required provisionally 12
Davicom Semiconductor
DM9161B X 1 0-31 0 provisionally provisionally
IC Plus Corp.
IP101ALF X 1 0-31 0 provisionally provisionally Link signal depends on PHY address.
IP101G X 1 0, 1, x 0 provisionally provisionally Link signal depends on PHY address. Max. 3 ports usable because of PHY addresses.
Marvell
88E3015/
88E3018
- - X 1 no 0-31 0 provisionally required
Micrel
KSZ8001L X X X 1 yes (Vendor) 1-31
ET1100/
ET1200: 0
IP: 16
provisionally
PHY addr. 0 = Broadcast.
ET1100/ET1200: if port 0 is used, set PHY addresses to 1-4, PHY address offset to 0. Disable
Enhanced link detection or add CPLD/uC for address conversion.
IP Core: Set PHY address offset = 16 and use PHY addresses 16-19.
The KSZ8001 might have a pull-up resistor at the MCLK pin, which might interfere with an external pull-
down resistor for strapping.
KSZ8041TL Rev. A4
KSZ8041NL Rev. A4
X X X 1 yes (Vendor) 1-7
ET1100/
ET1200: 0
IP: 1
10 µs recommended 11
PHY addr. 0 = Broadcast. Enable 8 byte preamble with CONFIG[2:0]=100 (was PCS Loopback in Rev.
A3).
ET1100/ET1200: if port 0 is used, set PHY addresses to 1-4, PHY address offset to 0. Disable
Enhanced link detection or add CPLD/uC for address conversion.
IP Core: Set PHY address offset = 1 and use PHY addresses 1-4.
The KSZ8041 might have a pull-up resistor at the MCLK pin, which might interfere with an external pull-
down resistor for strapping.
KSZ8051 MLL Rev. A2
KSZ8051 MNL Rev. A2
X X X 1 yes (Vendor) 0-7 0 5.3 µs recommended 11
Enable B_CAST_OFF to support PHY addr. 0 (otherwise PHY addr. 0 = Broadcast).
Rev. A2 has a fixed TX_CLK phase.
The KSZ8051 might have a pull-up resistor at the MCLK pin, which might interfere with an external pull-
down resistor for strapping.
KSZ8081MNX
KSZ8081MLX
X X X 1 yes (Data sheet) 0-7 0 4.4 µs recommended 11
Enable B_CAST_OFF to support PHY addr. 0 (otherwise PHY addr. 0 = Broadcast).
The KSZ8081 has a pull-up resistor at the MCLK pin, which might interfere with an external pull-down
resistor for strapping.
Realtek
RTL8201N - - X 1 no 1-31 16 provisionally required PHY addr. 0 = Power down.
RTL8201DL - - X 1 no 0-7 0 provisionally required
6 The following requirements were not part of the basic hardware test: MDI/MDI-X auto-crossover, MII management interface, TX clock phase relation, and preamble length maintenance. These requirements are assumed to be fulfilled either according to the data
sheet or vendor notice. Hardware tests are typically performed with only one of the ESC types, e.g., IP Core.
7 Information about fixed phase shift between TX_CLK and PHY clock source from data sheet or from vendor
8 PHY address range supported by PHY. Special PHY addresses are excluded (Broadcast/Isolate/Power down).
9 Suggested PHY address offset. ET1100 and ET1200 only support a PHY address offset of 0 or 16. A PHY address offset of 0 means PHY addresses 0-3 are used, an offset of 16 means PHY addresses 16-19 are used, etc..
10 Only for XTALI, not approved for REF_CLK. According to Broadcom, a quartz oscillator can be connected to XTALI as well.
11 Recommended for IP Core only. Do not enable for ET1100/ET1200.
12 Measurements from the vendor with some LXT973 indicated that there is a fixed TX_CLK phase relation, but a general statement could not be made. It is assumed that Auto-TX-Shift is not required and that ET1200/ET1100 are supported, but provisionally Auto-
TX-Shift should be turned on.