BECKHOFF PHY - Manual (Page 5)

Ethernet PHY Requirements
Slave Controller – Application Note PHY Selection Guide 2
2 Ethernet PHY Requirements
ESCs which support Ethernet Physical Layer use MII interfaces, some do also support the RMII interface. Since
RMII PHYs include TX FIFOs, they increase the forwarding delay of an EtherCAT slave device as well as the
jitter. RMII is not recommended due to these reasons.
EtherCAT and Beckhoff ESCs have some general requirements to Ethernet PHYs, which are typically fulfilled
by state-of-the-art Ethernet PHYs.
The MII interfaces of Beckhoff ESCs are optimized for low processing/forwarding delays by omitting a
transmit FIFO. To allow this, the Beckhoff ESCs have additional requirements to Ethernet PHYs, which
are easily accomplished by several PHY vendors.
Refer to Section III of the ESC documentation for ESC specific information about supported features.
Requirements to Ethernet PHYs used for EtherCAT:
 The PHYs have to comply with IEEE 802.3 100BaseTX or 100BaseFX.
 The PHYs have to support 100 Mbit/s Full Duplex links.
 The PHYs have to provide an MII (or RMII 1 ) interface.
 The PHYs have to use autonegotiation in 100BaseTX mode.
 The PHYs have to support the MII management interface.
 The PHYs have to support MDI/MDI-X auto-crossover in 100BaseTX mode.
 PHY link loss reaction time (link loss to link signal/LED output change) has to be faster than 15 µs to
enable redundancy operation
2 .
 The PHYs must not modify the preamble length.
 The PHYs must not use IEEE802.3az Energy Efficient Ethernet.
 The PHYs must offer the RX_ER signal (MII/RMII) or RX_ER as part of the RX_CTL signal (RGMII).
Additional requirements to Ethernet PHYs used with Beckhoff ESCs:
 The PHYs have to provide a signal indicating a 100 Mbit/s (Full Duplex) link 3 , typically a configurable
LED output. The signal polarity is active low or configurable for some ESCs.
 The PHY addresses should be equivalent to the logical port number (0-3). Some ESCs also support a
fixed offset (e.g. offset 16, PHY addresses are logical port number plus 16: 16-19), or even an arbitrary
offset. If none of these possibilities can be used, the PHY address should be configured to logical port
number plus 1 (1-4), although some features (e.g., Enhanced Link Detection) can not be used in this case,
because apart from the optional configurable PHY address offset, the PHY addresses are hard-coded inside
the ESCs.
 PHY configuration must not rely on configuration via the MII management interface, i.e., required features
have to be enabled after power-on, e.g., by default or by strapping options. PHY startup should not rely on
MII management interaction, i.e., MDC clocking, since many ESCs do not communicate with the PHY via
management interface unless the EtherCAT master requests this (only the EtherCAT IP Core with MI Link
detection and configuration will communicate without master interaction).
Additional requirements to Ethernet PHYs used with Beckhoff ESCs using the MII Interface:
 All PHYs connected to one ESC and the ESC itself must share the same clock source. This can be
achieved by sourcing the PHYs from an ESC clock output or by sourcing the PHYs and the ESC from the
same quartz oscillator. The ESC10/20 uses TX_CLK as a clock source, both PHYs have to share the same
quartz oscillator.
1 RMII is only supported by the EtherCAT IP Core
2 This can either be achieved by a PHY with such a link loss reaction time or by activating Enhanced link detection if the
PHY asserts RX_ER both inside and outside of frames for each invalid symbol. Enhanced link detection requires proper
PHY address configuration.
3 If a combined signal (100 MBit/s link with Full Duplex) is not available, a signal indicating 100 Mbit/s speed might be used.
Take care that the speed signal is inactive (10 Mbit/s) in case of no link. If only a Link signal is available, this might be used.
Never use (combined) activity signals. Some PHYs toggle the 100 Mbit/s speed signal during autonegotiation, this is a
problem for hot-connecting. Use the link signal in this case.
 The TX_CLK signals of the PHYs must have a fixed phase relation to the clock input of the PHYs with a
tolerance of ±5 ns
4 , because a TX FIFO is omitted. During operation the phase relation can not change
since the PHYs and the ESC have to share the same clock source. The phase offset is compensated inside
the ESC either manually by configuration or automatic:
Manual TX Shift compensation: ET1100, ET1200, and IP Core provide a TX Shift configuration option
(configurable TX_EN/TXD signal delay by 0/10/20/30 ns) which is used for all MII ports. Thus, all PHYs
connected to one ESC must have the same fixed phase relation between TX_CLK and their clock input.
This is typically true if the same PHY model is used for all ports. The phase relation has to be the same
each time the PHYs are powered on. As the ESC10/20 use TX_CLK as device clock source, configuration
is not necessary, but the requirements for manual TX Shift compensation have to be fulfilled anyway.
Automatic TX Shift compensation: The IP Core supports automatic TX Shift compensation individually for
each port. With automatic TX Shift compensation, the PHYs are not required to have the same fixed phase
relation each time they are powered on.
Recommendations to Ethernet PHYs used for EtherCAT:
 Receive and transmit delays should be deterministic, and as low as possible.
 Maximum cable length should be ≥ 120 m to maintain a safety margin if the standard maximum cable length
of 100 m is used.
 ESD tolerance should be as high as possible (4kV or better)
 Baseline wander should be compensated (the PHYs should cope with the ANSI X3.263 DDJ test pattern for
baseline wander measurements at maximum cable length)
 The PHYs should detect link loss within the link loss reaction time of 15 µs also if only one of the RX+ and
RX- lines gets disconnected.
 The PHYs should maintain the link state regardless of the received symbols, as long as the symbols are
valid.
 Ethernet PHYs for 100BaseFX should implement Far-End-Fault (FEF) completely (generation and
detection).
 MDC should not incorporate pull-up/pull-down resistors, as this signal is used as a configuration input signal
by some ESCs.
 Restriction of Autonegotiation advertisement to 100 Mbit/s / Full Duplex is desirable (configured by
hardware strapping options).
 Power consumption should be as low as possible.
 I/O voltage: 3.3V should be supported for current ASIC and FPGA ESCs, additional 2.5V/1.8V I/O support is
recommended for recent FPGA ESCs.
 Single power supply according to I/O voltage.
 The PHY should use a 25 MHz clock source (quartz oscillator or ESC output).
 Industrial temperature range should be supported.
NOTE: The following requirements defined by IEEE802.3 have to be observed:
a) the preamble length should be maintained. Accumulating preamble reduction below 2 bytes including Start-of-Frame-
Delimiter/SFD (0x55 5D) must not occur for single or cascaded ESCs. ESCs can not regenerate preambles to 8 bytes
including SFD because of the on-the-fly processing: received and transmitted preamble length is identical.
b) receive and transmit delays should comply with the standard (RX delay should be below ~320 ns, TX delay below ~140
ns),
c) MII Management interface should not require additional MCLK cycles or continuous MCLK.
Recommendations to FX transceivers used for EtherCAT:
 The transceiver should have an input for disabling the transceiver/transmitter (for Enhanced FX link
detection; e.g. enable, power-down or reset).
4 The ±5ns tolerance is valid for PHYs using the IEEE802.3 TX specification (TX signal change is allowed in a time window
of 25 ns, TX signals are stable in a window of 15 ns). If the PHY has a larger window for changing the TX signals (25 ns + x),
the tolerance will be ±(5ns + x/2).