Digi NS9210 - Manual (Page 25)

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C l o c k g e n e r a t i o n
Clock frequencies
Hardware strapping determines the initial powerup PLL settings. The table below
summarizes the default clock frequencies for the NS9210 Processor Module:
SW_CONF1 User-defined software
configuration pin; can be read in
GEN ID register bit 5, default
high Connected to A14 through a 2k2
series resistor.Read bit 5 of GEN
ID register (@ 0xA0900210).
SW_CONF2 User-defined software
configuration pin; can be read in
GEN ID register bit 6, default
high Connected to A15 through a 2k2
series resistor. Read bit 6 of GEN
ID register (@ 0xA0900210).
SW_CONF3 User-defined software
configuration pin; can be read in
GEN ID register bit 7, default
high Connected to A16 through a 2k2
series resistor. Read bit 7 of GEN
ID register (@ 0xA0900210).
Signal name Function PU/PD Comment
Hardware strapping:
"PLL reference clock divider setting:
A[4:0] = 0x1D (0b11101)
NR = 5
"PLL output divider setting:
A[6:5] = 0x3 (0b11)
OD = 0
"PLL bypass setting:
A[7] = 0x1 (0b1)
Normal operation
PLL frequency formula:
PLL Vco = (RefClk / NR+1) * (NF+1)
ClkOut = PLL Vco / (OD+1)
RefClk (Crystal) = 29.4912MHz
NF = 0x3C (reset value - can only be changed by software).
PLL Vco = (29.4912 / 6) * 61 = 299.8272 MHz
ClkOut = 299.8272 MHz
Resulting clock settings:
PIC clock = 299.8272 MHz