Measurement Computing ADAC-LVi - Manual (Page 148)

Chapter 2 Digital I/O Library
ADAC LabVIEW VI 142
$'$& 6HW  3RUW 6WUXFW FRQ¶W
1:AND All unmasked bit conditions must occur.
2:OR Any unmasked bit conditions must occur.
The default Port Mode Specification is 2:OR
Pattern Latch Pattern Latch controls the Latch On Pattern ability. If
the Pattern Latch is enabled, the state of the input port will be latched
when a match condition occurs. The data will be held until the port is
read within its interrupt handler. If a subsequent match occurs (port
goes from match condition to non-match condition to a new match
condition) before the port is read within its interrupt handler, an IP
error condition will occur stopping the acquisition. The Ignore IP Error
control can be set to TRUE to disable the IP error checking in the
driver, but data may be lost when match conditions are occurring faster
than they can be serviced.
Data Path Polarity Data Path Polarity allows each bit for DIN0 to be
individually inverted. If the associated bit is set "1", data read from that
bit on DIN0 will be inverted. For detailed definitions see the 5600
manuals ADVANCED PROGRAMMING TECHNIQUES. When the
Port Resolution is set for 16 bit mode, Data Path Polarity is set in
WORDs b(1111111111111111).
Special IO Control The SpecialIoControl controls the BIT CATCHER
operation mode. Port DIN0 may be configured to return the state of the
bit catcher, instead of the actual port data by setting the associated bit
to "1" in the Special Io Control. If a bit is so programmed, the port will
return "0" for that bit until a "1" occurs at the input. The port will then
read back a "1" even if the "1" goes away. When the DIN0 port is
serviced by the driver, each bit enabled and in the "1" state will read
automatically reset and ready for the next input transition. For detailed
definitions see the 5600 manuals ADVANCED PROGRAMMING
TECHNIQUES. When the Port Resolution is set for 16 bit mode,
Special Io Control is set in WORDs b(1111111111111111).
Pattern Polarity The PatternPolarity, PatternTransition and
PatternMask define the match condition for the Port Mode
Specification AND / OR modes.
For example on can define a match condition as bit 1, bit 2 and bit 3 all
set = "1" as a valid match (AND mode) by setting the following.
Port Mode Specification = AND
PatternPolarity = (b) 1110