Measurement Computing TempScan/1100 - Manual (Page 111)

TempScan / MultiScan User's Manual 889897 System Operation 5-21
• Error Indicators (Bits 0 to 5) in Calibration Modes (10 or 11): Any calibration error in any of the
four modes will be mapped into the
CSR
Bits 0 to 5, which together maps to the Calibration Error Bit
(Bit 3) in the Error Source Register (
ESC
). In either Calibration Mode, these same six bits are set as
follows:
Bit 5: Read Failure (EEPROM Error).
Bit 4: Write Failure (EEPROM Error).
Bit 3: Checksum Error (EEPROM Error).
Bit 2: Calibration Error. Set when the thermocouple offset or gain, or CJC (cold-junction
compensation) temperature sensor offset is outside of the valid range values, as follows:
-365
ASCII Counts (-50 mV) ≤≤≤≤ thermocouple offset ≤≤≤≤
+365
ASCII Counts (+50 mV)
-583
ASCII Counts (-80 mV) ≤≤≤≤ high-voltage offset ≤≤≤≤
+583
ASCII Counts (+80 mV)
+0.8
(ratio) ≤≤≤≤ thermocouple gain ≤≤≤≤
+1.2
(ratio)
-1000
ASCII Counts (-10 °C) ≤≤≤≤ CJC sensor offset ≤≤≤≤
+1000
ASCII Counts (+10 °C)
Bit 1: Invalid Password.
Bit 0: Invalid Command.
A checksum is used for validating the contents of memory. When the contents of memory is created, each
byte is summed and the least significant byte of the resultant sum is stored in a specific byte of memory.
This value is called the checksum. Then typically on power-up, the processor recomputes the checksum
and compares it to its stored known correct value. If the computed and stored checksums match, then the
memory is fine. Otherwise, if they do not match, then the memory became corrupt somehow. For example,
on power-up and during calibration, the TempScan/1100 unit computes the checksum on the chassis
calibration constants in NV-RAM, and on the EEPROMs of each installed scanning card. If any of the
checksum tests fail, the Checksum Bit (Bit 3) is set in the Calibration Status Register (
CSR
).
For more information on NV-RAM and EEPROMs, see section Calibration Properties in the chapter
System Calibration. For more information on the Calibration Status Register (
CSR
), see command User
Status (
U
).
Error Source Register (ESC)
The Error Source Register (
ESC
) is a Read/Clear-Only register in that they may only be read and cleared by
the controller, via the Query Error Status (E?) command. The read operation is a destructive read since it
clears the register as it is read. This register can only be written to by internal TempScan/1100 or
MultiScan/1200 operations.
The Error Source Register (
ESC
) indicates which general errors, if any, have occurred. Its bits and the
errors that set them, are as follows:
• Command Conflict Error (Bit 7): Set when an issued command is in conflict with other issued
commands or with the current configuration. This error usually occurs when an issued command
cannot be performed because it is incompatible with the current state of the TempScan/1100 or
MultiScan/1200 unit. This bit is one of the
ESC
Bits 2 to 7, which together maps to the Execution Error
Bit (Bit 4) in the Event Status Register (
ESR
).
• Open Thermocouple or Range Error (Bit 5): Set when the hardware circuitry detects an open
thermocouple, or the software routines detect either that the input A/D data has reached its maximum
value or the input data has exceeded its linearization limits. This bit is one of the
ESC
Bits 2 to 7,
which together maps to the Execution Error Bit (Bit 4) in the
ESR
.
• Trigger Overrun (Bit 4): Set when more than one Trigger (trigger start event) or more than one Stop
(trigger stop event) occurs during one Trigger Block acquisition, or when when an unexpected Trigger
occurs. This bit is one of the
ESC
Bits 2 to 7, which together maps to the Execution Error Bit (Bit 4) in
the
ESR
.
• Calibration Error (Bit 3): Set when the calibration is inappropriate or has failed. The Error Indicator
Bits (Bits 0 to 5) in the Calibration Status Register (
CSR
) together map to this bit. This bit is one of the
ESC
Bits 2 to 7, which together maps to the Execution Error Bit (Bit 4) in the
ESR
.