Sundance SMT381 2004 - Manual (Page 73)

1 1 W/R
7 Address bits
64 Data bits
Table 14. Configuration of the DACSerialSetupReg register.
The W/R in the last bit selects between a ‘write’ and a ‘read’ cycle.
The following figure shows the DAC state machine.
Figure 65. State machine of the DAC for the SMT381.
The state machine works in 5 stages:
•
Initialisation
•
Address clocked out
•
Clock out write or read bit
•
Data clocked out
•
End sequence