Sundance SMT398VP User Manual
Smt398vp, User guide for
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Table of contents
Document Outline
- APPROVAL PAGE
- AUTHOR/S
- DOCUMENT HISTORY
- TABLE OF CONTENTS
- TABLE OF FIGURES
- TABLE OF TABLES
- 1. SCOPE
- 2. APPLICABLE DOCUMENTS AND REFERENCES
- 3. ACRONYMS, ABBREVIATIONS AND DEFINITIONS
- 4. FEATURES
- 4.1. THE SMT398VP TIM
- 4.1.1. SMT398VP Diagram
- 4.1.2. Interface Definition
- 4.1.3. Major features
- 4.1.4. Prime Item Characteristics
- 4.1.4.1. FPGA
- 4.1.4.2. CPLD
- 4.1.4.3. PROM
- 4.1.4.4. JTAG Header
- 4.1.4.5. FPGA Configuration schemes
- 4.1.4.6. FPGA Reset Scheme
- 4.1.4.7. QDR II SRAM
- 4.1.4.8. Sundance High speed Bus
- 4.1.4.9. Sundance Low voltage Bus
- 4.1.4.10. Sundance Rocket io Serial Link
- 4.1.4.11. TIM Connectors
- 4.1.4.12. DIP Switches
- 4.1.4.13. Clocking scheme
- 4.1.4.14. Leds
- 4.1.5. Performance
- 4.1.6. Physical Characteristics
- 4.1. THE SMT398VP TIM
- 5. FOOTPRINT
- 6. PINOUT
- 7. ORDERING INFORMATION
- 8. QUALIFICATION REQUIREMENTS
- 9. HARDWARE SUPPORT PACKAGE