Teac VRDS-701T 70th Anniversary CD Transport (Black) - Manual (Page 108)

108
Diagrama de bloques
Master Clock
FPGA
ΔΣ Modulator
S/PDIF
S/PDIF
I2S
TEAC
VRDS CD Mechanism
PCM/ DSD
I2S
MUX
S/PDIF
COAXIAL
In
OPTICAL
In
USB-C
S/PDIF
COAX Out OPT Out
Crystal OSC 45.1584
MHz
External 10MHz In
Master Clock
Master Clock
Clock Sync
Circuit
Digital
Audio
I/F
Transmitter
D/A
Data/Clock
D/A
Data/Clock
D/A
Data/Clock
D/A
Data/Clock
LPF LPF LPF LPF
TEAC QVCS
HCLD2 HCLD2 HCLD2
XLR RCA
Selector
TEAC QVCS
HCLD2 HCLD2
XLR RCA
Selector
HCLD2
Phone
TEAC
ΔΣ Discrete DAC
XLR
Analog Out
RCA
Analog Out
RCA
Analog Out
XLR
Analog Out
Crystal OSC 49.152 MHz
Output PCB
USB I/F
MQA
Decoder