Document Outline

• 1 Introduction
  • 1.1 Overview
  • 1.2 Processor Abstraction Layer
  • 1.3 Mixing Processors of Different Frequencies and Cache Sizes
  • 1.4 Terminology
  • 1.5 State of Data
  • 1.6 Reference Documents
• 2 Electrical Specifications
  • 2.1 Itanium® 2 Processor System Bus
    • 2.1.1 System Bus Power Pins
    • 2.1.2 System Bus No Connect
  • 2.2 System Bus Signals
    • 2.2.1 Signal Groups
    • 2.2.2 Signal Descriptions
  • 2.3 Package Specifications
  • 2.4 Signal Specifications
    • 2.4.1 Maximum Ratings
  • 2.5 System Bus Signal Quality Specifications and Measurement Guidelines
    • 2.5.1 Overshoot/Undershoot Magnitude
    • 2.5.2 Overshoot/Undershoot Pulse Duration
    • 2.5.3 Activity Factor
    • 2.5.4 Reading Overshoot/Undershoot Specification Tables
    • 2.5.5 Determining if a System Meets the Overshoot/Undershoot Specifications
    • 2.5.6 Wired-OR Signals
  • 2.6 Power Pod Connector Signals
  • 2.7 Itanium® 2 Processor System Bus Clock and Processor Clocking
  • 2.8 Recommended Connections for Unused Pins
• 3 Pinout Specifications
• 4 Mechanical Specifications
  • 4.1 Mechanical Dimensions
  • 4.2 Package Marking
    • 4.2.1 Processor Top-Side Marking
    • 4.2.2 Processor Bottom-Side Marking
• 5 Thermal Specifications
  • 5.1 Thermal Features
    • 5.1.1 Thermal Alert
    • 5.1.2 Enhanced Thermal Management
    • 5.1.3 Thermal Trip
  • 5.2 Case Temperature
• 6 System Management Feature Specifications
  • 6.1 System Management Bus
    • 6.1.1 System Management Bus Interface
    • 6.1.2 System Management Interface Signals
    • 6.1.3 SMBus Device Addressing
  • 6.2 Processor Information ROM
  • 6.3 Scratch EEPROM
  • 6.4 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions
  • 6.5 Thermal Sensing Device
  • 6.6 Thermal Sensing Device Supported SMBus Transactions
  • 6.7 Thermal Sensing Device Registers
    • 6.7.1 Thermal Reference Registers
    • 6.7.2 Thermal Limit Registers
    • 6.7.3 Status Register
    • 6.7.4 Configuration Register
    • 6.7.5 Conversion Rate Register
• A Signals Reference
  • A.1 Alphabetical Signals Reference
    • A.1.1 A[49:3]# (I/O)
    • A.1.2 A20M# (I)
    • A.1.3 ADS# (I/O)
    • A.1.4 AP[1:0]# (I/O)
    • A.1.5 ASZ[1:0]# (I/O)
    • A.1.6 ATTR[3:0]# (I/O)
    • A.1.7 BCLKp/BCLKn (I)
    • A.1.8 BE[7:0]# (I/O)
    • A.1.9 BERR# (I/O)
    • A.1.10 BINIT# (I/O)
    • A.1.11 BNR# (I/O)
    • A.1.12 BPM[5:0]# (I/O)
    • A.1.13 BPRI# (I)
    • A.1.14 BR[0]# (I/O) and BR[3:1]# (I)
    • A.1.15 BREQ[3:0]# (I/O)
    • A.1.16 CCL# (I/O)
    • A.1.17 CPUPRES# (O)
    • A.1.18 D[127:0]# (I/O)
    • A.1.19 D/C# (I/O)
    • A.1.20 DBSY# (I/O)
    • A.1.21 DBSY_C1# (O)
    • A.1.22 DBSY_C2# (O)
    • A.1.23 DEFER# (I)
    • A.1.24 DEN# (I/O)
    • A.1.25 DEP[15:0]# (I/O)
    • A.1.26 DHIT# (I)
    • A.1.27 DPS# (I/O)
    • A.1.28 DRDY# (I/O)
    • A.1.29 DRDY_C1# (O)
    • A.1.30 DRDY_C2# (O)
    • A.1.31 DSZ[1:0]# (I/O)
    • A.1.32 EXF[4:0]# (I/O)
    • A.1.33 FCL# (I/O)
    • A.1.34 FERR# (O)
    • A.1.35 GSEQ# (I)
    • A.1.36 HIT# (I/O) and HITM# (I/O)
    • A.1.37 ID[9:0]# (I)
    • A.1.38 IDS# (I)
    • A.1.39 IGNNE# (I)
    • A.1.40 INIT# (I)
    • A.1.41 INT (I)
    • A.1.42 IP[1:0]# (I)
    • A.1.43 LEN[2:0]# (I/O)
    • A.1.44 LINT[1:0] (I)
    • A.1.45 LOCK# (I/O)
    • A.1.46 NMI (I)
    • A.1.47 OWN# (I/O)
    • A.1.48 PMI# (I)
    • A.1.49 PWRGOOD (I)
    • A.1.50 REQ[5:0]# (I/O)
    • A.1.51 RESET# (I)
    • A.1.52 RP# (I/O)
    • A.1.53 RS[2:0]# (I)
    • A.1.54 RSP# (I)
    • A.1.55 SBSY# (I/O)
    • A.1.56 SBSY_C1# (O)
    • A.1.57 SBSY_C2# (O)
    • A.1.58 SPLCK# (I/O)
    • A.1.59 STBn[7:0]# and STBp[7:0]# (I/O)
    • A.1.60 TCK (I)
    • A.1.61 TDI (I)
    • A.1.62 TDO (O)
    • A.1.63 THRMTRIP# (O)
    • A.1.64 THRMALERT# (O)
    • A.1.65 TMS (I)
    • A.1.66 TND# (I/O)
    • A.1.67 TRDY# (I)
    • A.1.68 TRST# (I)
    • A.1.69 WSNP# (I/O)
  • A.2 Signal Summaries