Intel Itanium 2 Processor - Manual (Page 18)

18 Datasheet
Electrical Specifications
2.4 Signal Specifications
This section describes the DC specifications of the system bus signals. The processor signal’s DC
specifications are defined at the Itanium 2 processor pins.
Table 2-4 through Table 2-9 describe the
DC specifications for the AGTL+, PWRGOOD, HSTL clock, TAP port, system management, and
LVTTL signals. Please refer to the ITP700 Debug Port Design Guide for the TAP connection
signals DC specifications at the debug port.
NOTES:
1. This is the tolerance requirement, across a 200 MHz bandwidth, at the processor pins. The requirement at the processor pins
accounts for voltage drops (and impedance discontinuities) at the processor pins and to the processor core. In addition to the
±1.5% DC tolerance, there is a ±3.5% AC tolerance for a total of ±5% tolerance.
2. The Itanium ® 2 processor system bus is terminated at each end of the system bus. The Itanium 2 processor supports both on-
die and off-die termination which is selected by the TERMA and TERMB pins. Termination tolerance is ±15% for on-die
termination measured at V
OL
and ±1% for off-die termination.
3. Maximum termination voltage current on one terminating agent.
4. For all core frequencies and cache sizes.
5. Maximum thermal design envelope is provided for the design of thermal/chassis solutions.
6. Maximum thermal design power is an estimate of the power dissipation for the Itanium 2 processor offering while executing a
worst-case application mix under nominal V
CC,PS
and worst-case temperature.
Table 2-3. Itanium
®
2 Processor Power Supply Specifications
Symbol Parameter Minimum Typ Maximum Unit Notes
V
CC,PS
V
CC
from the Power Supply VID –1.5% VID VID +1.5% V 1, 2
NOTES:
1. The power pod DC set point accuracy is ±1.5%. Included for reference only, under worst case switching activity, the power pod
tolerance is ±7%.
2. The V
CC,PS
for the processor is defined by the VID bits specified in Table 2-23 .
I
CC,PS
Current Required from Power Supply 100 A 3
3. The maximum current (I
CC,PS
) specification is intended for system power supply design. The maximum current values are
defined to be based on worst-case V
CC,PS
, temperature and application mix.
PS
slew_rate
Power Supply Slew Rate at the
Processor Power Pod Connector 100 A/µs
PS
TT
Power Supply Slew Rate for the
Termination Voltage at the Processor
Pins 0.05 A/ns
Table 2-4. AGTL+ Signals DC Specifications (Sheet 1 of 2)
Symbol Parameter
Core
Frequency
Minimum Typ Maximum Unit Notes
V
IL
Input Low Voltage All 0.625 V 1
V
IH
Input High Voltage All 0.875 V 1
V
IL
Input Low Voltage
(1.6x GHz, I.5 GHz/4 MB
Itanium
® 2 Processors)
All 0.65 V 1
V
IH
Input High Voltage
(1.6x GHz, I.5 GHz/4 MB
Itanium 2 Processors) All 0.85 V
1
V
OL
Output Low Voltage All 0.3 0.4 V 2
V
OH
Output High Voltage All V
CTERM
,
minimum
V
CTERM
V
CTERM
,
maximum
V
I
OL
Output Low Current @ 0.3V All 34 mA 3
I
OL
Output Low Current @ 0.3V All 17 mA 4