Intel Itanium 2 Processor - Manual (Page 9)

Datasheet 9
Intel
®
Itanium
®
2 Processor
Intel
®
Itanium
®
2 Processor 1.66 GHz with 9 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.66 GHz with 6 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.6 GHz with 9 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.6 GHz with 6 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.5 GHz with 6 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.5 GHz with 4 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.4 GHz with 4 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.3 GHz with 3 MB L3 Cache
Intel
®
Itanium
®
2 Processor 1.0 GHz with 3 MB L3 Cache
Intel
®
Itanium
®
2 Processor 900 MHz with 1.5 MB L3 Cache
Product Features
The Intel
®
Itanium
®
2 processor is designed to address the needs of high-performance servers and workstations.
The Itanium architecture goes beyond RISC and CISC approaches by employing Explicitly Parallel Instruction
Computing (EPIC), which pairs extensive processing resources with intelligent compilers that enable parallel
execution explicit to the processor. The processor’s large internal resources combine with predication and
speculation to enable optimization for high performance applications running on multiple operating systems,
including versions of Microsoft Windows*, HP-UX* and Linux*. The Itanium 2 processor is designed to support
very large scale systems, including those employing thousands of processors, to provide the processing power and
performance head room for the most demanding enterprise and technical computing applications. SMBus
compatibility and comprehensive reliability, availability and serviceability (RAS) features make the Itanium 2
processor ideal for applications requiring high up-time. For high performance servers and workstations, the
Itanium 2 processor offers outstanding performance and reliability for today’s applications and the scalability to
address the growing e-business needs of tomorrow.
■ Wide, parallel hardware based on Intel
®
Itanium
®
architecture for high performance:
— Integrated on-die cache of up to 9 MB; cache
hints for L1, L2, and L3 caches for reduced
memory latency.
— 128 general and 128 floating-point registers
supporting register rotation.
— Register stack engine for effective management
of processor resources.
— Support for predication and speculation.
■ Extensive RAS features for business-critical
applications:
— Full SMBus compatibility.
— Enhanced machine check architecture with
extensive ECC and parity protection.
— Enhanced thermal management.
— Built-in processor information ROM (PIROM).
— Built-in programmable EEPROM.
■ High bandwidth system bus for multiprocessor
scalability:
— Up to 10.6 GB/s bandwidth.
— 128-bit wide data bus.
— 50-bits of physical memory addressing and 64-
bits of virtual addressing.
— Up to four processors on the same system bus at
400 MHz data bus frequency.
— Up to two processors on the same system bus at
533 MHz or 667 MHz data bus frequency.
— Expandable to systems with multiple system
buses.
■ Features to support flexible platform environments:
— Support for IA-32 application binaries.
— Bi-endian support.
— Processor abstraction layer eliminates processor
dependencies.