Intel Itanium 2 Processor - Manual (Page 5)

Datasheet 5
A.1.37 ID[9:0]# (I) .............................................................................................. 99
A.1.38 IDS# (I) ................................................................................................... 99
A.1.39 IGNNE# (I)............................................................................................100
A.1.40 INIT# (I) ................................................................................................ 100
A.1.41 INT (I) ................................................................................................... 100
A.1.42 IP[1:0]# (I)............................................................................................. 100
A.1.43 LEN[2:0]# (I/O) ..................................................................................... 100
A.1.44 LINT[1:0] (I) .......................................................................................... 101
A.1.45 LOCK# (I/O) ......................................................................................... 101
A.1.46 NMI (I) .................................................................................................. 101
A.1.47 OWN# (I/O) .......................................................................................... 101
A.1.48 PMI# (I)................................................................................................. 101
A.1.49 PWRGOOD (I)...................................................................................... 101
A.1.50 REQ[5:0]# (I/O) .................................................................................... 101
A.1.51 RESET# (I) ........................................................................................... 102
A.1.52 RP# (I/O) .............................................................................................. 102
A.1.53 RS[2:0]# (I) ........................................................................................... 103
A.1.54 RSP# (I)................................................................................................ 103
A.1.55 SBSY# (I/O).......................................................................................... 103
A.1.56 SBSY_C1# (O) ..................................................................................... 103
A.1.57 SBSY_C2# (O) ..................................................................................... 103
A.1.58 SPLCK# (I/O) ....................................................................................... 103
A.1.59 STBn[7:0]# and STBp[7:0]# (I/O) ......................................................... 104
A.1.60 TCK (I).................................................................................................. 104
A.1.61 TDI (I) ................................................................................................... 104
A.1.62 TDO (O)................................................................................................ 104
A.1.63 THRMTRIP# (O)................................................................................... 104
A.1.64 THRMALERT# (O) ............................................................................... 105
A.1.65 TMS (I) ................................................................................................. 105
A.1.66 TND# (I/O)............................................................................................105
A.1.67 TRDY# (I) ............................................................................................. 105
A.1.68 TRST# (I).............................................................................................. 105
A.1.69 WSNP# (I/O) ........................................................................................ 105
A.2 Signal Summaries ............................................................................................. 105
Figures
2-1 Generic Clock Waveform .................................................................................... 22
2-2 SMSC Clock Waveform....................................................................................... 22
2-3 System Bus Signal Waveform Exhibiting Overshoot/Undershoot ....................... 24
2-4 Itanium
®
2 Processor Power Tab Physical Layout.............................................. 30
2-5 Processor Full, Normal and Low Power Mode with Timings ............................... 32
2-6 System Bus Reset and Configuration Timings for Cold Reset............................ 34
2-7 System Bus Reset and Configuration Timings for Warm Reset.......................... 35
3-1 Itanium
®
2 Processor Pinout ............................................................................... 37
4-1 Itanium
®
2 Processor Package ........................................................................... 69
4-2 Itanium
®
2 Processor Package ........................................................................... 70
4-3 Itanium
®
2 Processor Package Power Tab ......................................................... 71
4-4 Processor Top-Side Marking on IHS................................................................... 72
4-5 Processor Bottom-Side Marking Placement on Interposer ................................. 73
5-1 Itanium
®
2 Processor Thermal Features ............................................................. 75