Intel Itanium 2 Processor - Manual (Page 103)

Datasheet 103
Signals Reference
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered
signals are high.
A.1.53 RS[2:0]# (I)
The Response Status (RS[2:0]#) signals are driven by the responding agent (the agent responsible
for completion of the transaction).
A.1.54 RSP# (I)
The Response Parity (RSP#) signal is driven by the responding agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP#
provides parity protection.
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. During the Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also
high since it is not driven by any agent guaranteeing correct parity.
A.1.55 SBSY# (I/O)
The Strobe Bus Busy (SBSY#) signal is driven by the agent transferring data when it owns the
strobe bus. SBSY# holds the strobe bus before the first DRDY# and between DRDY# assertions
for a multiple clock data transfer. SBSY# is deasserted before DBSY# to allow the next data
transfer agent to predrive the strobes before the data bus is released.
SBSY# is replicated three times to enable partitioning of data paths in the system agents. This copy
of the Strobe Bus Busy signal (SBSY#) is an input as well as an output.
A.1.56 SBSY_C1# (O)
SBSY# is a copy of the Strobe Bus Busy signal. This copy of the Strobe Bus Busy signal
(SBSY_C1#) is an output only.
A.1.57 SBSY_C2# (O)
SBSY# is a copy of the Strobe Bus Busy signal. This copy of the Strobe Bus Busy signal
(SBSY_C2#) is an output only.
A.1.58 SPLCK# (I/O)
The Split Lock (SPLCK#) signal is driven in the second clock of the Request Phase on the Ab[6]#
pin of the first transaction of a locked operation. It is driven to indicate that the locked operation
will consist of four locked transactions.