Document Outline

• 1.0 General Description
• 2.0 Features
• 3.0 Device Overview
  • 3.1 CR16C CPU Core
  • 3.2 Memory
  • 3.3 Input/Output Ports
  • 3.4 Bus Interface Unit
  • 3.5 Interrupt Control Unit (ICU)
  • 3.6 Multi-Input Wake-up
  • 3.7 Bluetooth LLC
  • 3.8 USB
  • 3.9 CAN Interface
  • 3.10 Quad UART
  • 3.11 Advanced Audio interface
  • 3.12 CVSD/PCM Conversion Module
  • 3.13 12-bit Analog to Digital Converter
  • 3.14 Random Number Generator
  • 3.15 Microwire/SPI
  • 3.16 ACCESS.bus Interface
  • 3.17 Multi-Function Timer
  • 3.18 Timing and Watchdog Module
  • 3.19 Versatile Timer Unit
  • 3.20 Triple Clock and Reset
  • 3.21 Power Management
  • 3.22 DMA Controller
  • 3.23 Serial Debug Interface
  • 3.24 Development Support
• 4.0 Signal Descriptions
• 5.0 CPU Architecture
  • 5.1 General-Purpose Registers
  • 5.2 Dedicated Address Registers
  • 5.3 Processor Status Register (PSR)
  • 5.4 Configuration Register (CFG)
  • 5.5 Addressing Modes
  • 5.6 Stacks
  • 5.7 Instruction Set
• 6.0 Memory
  • 6.1 Operating Environment
  • 6.2 Bus Interface Unit (BIU)
  • 6.3 Bus Cycles
  • 6.4 BIU Control Registers
  • 6.5 Wait and Hold States
• 7.0 System Configuration Registers
  • 7.1 Module Configuration Register (MCFG)
  • 7.2 Module Status Register (MSTAT)
  • 7.3 Software Reset Register (SWRESET)
• 8.0 Flash Memory
  • 8.1 Flash Memory Protection
  • 8.2 Flash Memory Organization
  • 8.3 Flash Memory Operations
  • 8.4 Information Block Words
  • 8.5 Flash Memory Interface Registers
• 9.0 DMA Controller
  • 9.1 Channel Assignment
  • 9.2 Transfer Types
  • 9.3 Operation Modes
  • 9.4 Software DMA Request
  • 9.5 Debug Mode
  • 9.6 DMA Controller Register Set
• 10.0 Interrupts
  • 10.1 Non-Maskable Interrupts
  • 10.2 Maskable Interrupts
  • 10.3 Interrupt Controller Registers
  • 10.4 Maskable Interrupt Sources
  • 10.5 Nested Interrupts
• 11.0 Triple Clock and Reset
  • 11.1 External Crystal Network
  • 11.2 Main Clock
  • 11.3 Slow Clock
  • 11.4 PLL Clock
  • 11.5 System Clock
  • 11.6 Auxiliary Clocks
  • 11.7 Power-On Reset
  • 11.8 External Reset
  • 11.9 Clock and Reset Registers
• 12.0 Power Management
  • 12.1 Active Mode
  • 12.2 Power Save Mode
  • 12.3 Idle Mode
  • 12.4 Halt Mode
  • 12.5 Hardware Clock Control
  • 12.6 Power Management Registers
  • 12.7 Switching Between Power Modes
• 13.0 Multi-Input Wake-Up
  • 13.1 Multi-Input Wake-Up Registers
  • 13.2 Programming Procedures
• 14.0 Input/Output Ports
  • 14.1 Port Registers
  • 14.2 Open-Drain Operation
• 15.0 Bluetooth Controller
  • 15.1 RF Interface
  • 15.2 Serial Interface
  • 15.3 LMX5251 Power-Up Sequence
  • 15.4 LMX5252 Power-Up Sequence
  • 15.5 Bluetooth Sleep Mode
  • 15.6 Bluetooth Global Registers
  • 15.7 Bluetooth Sequencer RAM
  • 15.8 Bluetooth Shared Data RAM
• 16.0 12-Bit Analog to Digital Converter
  • 16.1 Functional Description
  • 16.2 Touchscreen Interface
  • 16.3 ADC Operation in Power-Saving Modes
  • 16.4 Freeze
  • 16.5 ADC Register Set
• 17.0 Random Number Generator (RNG)
  • 17.1 Freeze
  • 17.2 Random Number Generator Register Set
• 18.0 USB Controller
  • 18.1 Functional States
  • 18.2 Endpoint Operation
  • 18.3 USB Controller Registers
  • 18.4 Transceiver Interface
• 19.0 CAN Module
  • 19.1 Functional Description
  • 19.2 Basic CAN Concepts
  • 19.3 Message Transfer
  • 19.4 Acceptance Filtering
  • 19.5 Receive Structure
  • 19.6 Transmit Structure
  • 19.7 Interrupts
  • 19.8 Time Stamp Counter
  • 19.9 Memory Organization
  • 19.10 CAN Controller Registers
  • 19.11 System Start-Up and Multi-Input Wake-Up
  • 19.12 Usage Hint
• 20.0 Advanced Audio Interface
  • 20.1 Audio Interface Signals
  • 20.2 Audio Interface Modes
  • 20.3 Bit Clock Generation
  • 20.4 Frame Clock Generation
  • 20.5 Audio Interface Operation
  • 20.6 Communication Options
  • 20.7 Audio Interface Registers
• 21.0 CVSD/PCM Conversion Module
  • 21.1 Operation
  • 21.2 PCM Conversions
  • 21.3 CVSD Conversion
  • 21.4 PCM to CVSD Conversion
  • 21.5 CVSD to PCM Conversion
  • 21.6 Interrupt Generation
  • 21.7 DMA Support
  • 21.8 Freeze
  • 21.9 CVSD/PCM Converter Registers
• 22.0 UART Modules
  • 22.1 Functional Overview
  • 22.2 UART Operation
  • 22.3 UART Registers
  • 22.4 Baud Rate Calculations
• 23.0 Microwire/SPI Interface
  • 23.1 Microwire Operation
  • 23.2 Master Mode
  • 23.3 Slave Mode
  • 23.4 Interrupt Generation
  • 23.5 Microwire Interface Registers
• 24.0 ACCESS.bus Interface
  • 24.1 ACB Protocol Overview
  • 24.2 ACB Functional Description
  • 24.3 ACCESS.bus Interface Registers
  • 24.4 Usage Hints
• 25.0 Timing and Watchdog Module
  • 25.1 TWM Structure
  • 25.2 Timer T0 Operation
  • 25.3 Watchdog Operation
  • 25.4 TWM Registers
  • 25.5 Watchdog Programming Procedure
• 26.0 Multi-Function Timer
  • 26.1 Timer Structure
  • 26.2 Timer Operating Modes
  • 26.3 Timer Interrupts
  • 26.4 Timer I/O Functions
  • 26.5 Timer Registers
• 27.0 Versatile Timer Unit (VTU)
  • 27.1 VTU Functional Description
  • 27.2 VTU Registers
• 28.0 Register Map
• 29.0 Register Bit Fields
• 30.0 Electrical Characteristics
  • 30.1 Absolute Maximum Ratings
  • 30.2 DC Electrical Characteristics (Temperature: -40˚C £ TA £ +85˚C)
  • 30.3 USB Transceiver Electrical Characteristics (Temperature: -40˚C £ TA £ +85˚C)
  • 30.4 ADC Electrical Characteristics (Temperature: -40˚C £ TA £ +85˚C)
  • 30.5 Flash Memory On-Chip Programming
  • 30.6 Output Signal Levels
  • 30.7 Clock and Reset Timing
  • 30.8 UART Timing
  • 30.9 I/O Port Timing
  • 30.10 Advanced Audio Interface (AAI) Timing
  • 30.11 Microwire/SPI Timing
  • 30.12 ACCESS.bus Timing
  • 30.13 USB Port AC Characteristics
  • 30.14 Multi-Function Timer (MFT) Timing
  • 30.15 Versatile Timing Unit (VTU) Timing
  • 30.16 External Bus Timing
• 31.0 Pin Assignments
  • 31.1 LQFP-128 Package
  • 31.2 LQFP-144 Package
• 32.0 Revision History
• 33.0 Physical Dimensions (millimeters) unless otherwise noted