National CP3BT26 - Manual (Page 17)

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CP3
BT26
5.4 CONFIGURATION REGISTER (CFG)
The CFG register is used to enable or disable various oper-
ating modes and to control optional on-chip caches. Be-
cause the CP3BT26 does not have cache memory, the
cache control bits in the CFG register are reserved. All CFG
bits are cleared on reset.
ED The Extended Dispatch bit selects whether
the size of an entry in the interrupt dispatch ta-
ble (IDT) is 16 or 32 bits. Each entry holds the
address of the appropriate exception handler.
When the IDT has 16-bit entries, and all ex-
ception handlers must reside in the first 128K
of the address space. The location of the IDT
is held in the INTBASE register, which is not
affected by the state of the ED bit.
0
– Interrupt dispatch table has 16-bit entries.
1 – Interrupt dispatch table has 32-bit entries.
SR The Short Register bit enables a compatibility
mode for the CR16B large model. In the
CR16C core, registers R12, R13, and RA are
extended to 32 bits. In the CR16B large mod-
el, only the lower 16 bits of these registers are
used, and these “short registers” are paired
together for 32-bit operations. In this mode,
the (RA, R13) register pair is used as the ex-
tended RA register, and address displace-
ments relative to a single register are
supported with offsets of 0 and 14 bits in place
of the index addressing with these displace-
ments.
0
– 32-bit registers are used.
1 – 16-bit registers are used (CR16B mode).
15 10 9 8 7 6 5 2 1 0
Reserved SR ED 0 0 Reserved 0 0