Cp3bt26 – National CP3BT26 User Manual

Page 116

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116

CP3BT26

Error Active

An error active unit can participate in bus communication
and may send an active (“dominant”) error flag.

Error Warning

The Error Warning state is a sub-state of Error Active to in-
dicate a heavily disturbed bus. The CAN module behaves
as in Error Active mode. The device is reset into the Error
Active mode if the value of both counters is less than 96.

Error Passive

An error passive unit can participate in bus communication.
However, if the unit detects an error it is not allowed to send
an active error flag. The unit sends only a passive (“reces-
sive”) error flag. A device is error passive when the transmit
error counter or the receive error counter is greater than
127. A device becoming error passive will send an active er-
ror flag. An error passive device becomes error active again
when both transmit and receive error counter are less than
128.

Bus Off

A unit that is bus off has the output drivers disabled, i.e., it
does not participate in any bus activity. A device is bus off

when the transmit error counter is greater than 255. A bus
off device will become error active again after monitoring
128 × 11 “recessive” bits (including bus idle) on the bus.
When the device goes from “bus off“ to “error active“, both
error counters will have a value of 0.

19.2.5

Error Counters

There are multiple mechanisms in the CAN protocol to de-
tect errors and inhibit erroneous modules from disabling all
bus activities. Each CAN module includes two error
counters to perform error management. The receive error
counter (REC) and the transmit error counter (TEC) are 8-
bits wide, located in the 16-bit wide CANEC register. The
counters are modified by the CAN module according to the
rules listed in Table 45. This table provides an overview of
the CAN error conditions and the behavior of the CAN mod-
ule; for a detailed description of the error management and
fault confinement rules, refer to the CAN Specification 2.0B.

If the MSB (bit 7) of the REC is set, the node is error passive
and the REC will not increment any further.

The Error counters can be read by application software as
described under CAN Error Counter Register (CANEC) on
page 139.

Special error handling for the TEC counter is performed in
the following situations:

„ A stuff error occurs during arbitration, when a transmitted

“recessive” stuff bit is received as a “dominant” bit. This
does not lead to an increment of the TEC.

„ An ACK-error occurs in an error passive device and no

“dominant” bits are detected while sending the passive
error flag. This does not lead to an increment of the TEC.

„ If only one device is on the bus and this device transmits

a message, it will get no acknowledgment. This will be
detected as an error and the message will be repeated.
When the device goes “error passive” and detects an ac-
knowledge error, the TEC counter is not incremented.
Therefore the device will not go from ”error passive” to
the “bus off” state due to such a condition.

Table 45

Error Counter Handling

Condition

Action

Receive Error Counter Conditions

A receiver detects a bit error during sending an active error flag.

Increment by 8

A receiver detects a “dominant“ bit as the first bit after sending an error flag

Increment by 8

After detecting the 14th consecutive “dominant“ bit following an active error flag or overload
flag, or after detecting the 8th consecutive “dominant“ bit following a passive error flag.
After each sequence of additional 8 consecutive “dominant” bits.

Increment by 8

Any other error condition (stuff, frame, CRC, ACK)

Increment by 1

A valid reception or transmission

Decrement by 1 unless
counter is already 0

Transmit Error Counter Conditions

A transmitter detects a bit error while sending an active error flag

Increment by 8

After detecting the 14th consecutive “dominant“ bit following an active error flag or overload
flag or after detecting the 8th consecutive “dominant“ bit following a passive error flag.
After each sequence of additional 8 consecutive ‘dominant’ bits.

Increment by 8

Any other error condition (stuff, frame, CRC, ACK)

Increment by 8

A valid reception or transmission

Decrement by 1 unless
counter is already 0

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