National CP3BT26 - Manual (Page 58)

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CP3BT26
HALT The Halt Mode bit indicates whether the de-
vice is in Halt mode. Before entering Halt
mode, the WBPSM bit must be set. When the
HALT bit is written with 1, the device enters
the Halt mode at the execution of the next
WAIT instruction. When in HALT mode, the
PMM stops the System Clock and then turns
off the PLL and the high-frequency oscillator.
The HALT bit can be set and cleared by soft-
ware. The Halt mode is exited by a hardware
wake-up event. When this signal is set high,
the oscillator is started. After the oscillator has
stabilized, the HALT bit is cleared by the hard-
ware.
0
– Device is not in Halt mode.
1 – Device is in Halt mode.
WBPSM When the Wait Before Power Save Mode bit is
clear, a switch from Active mode to Power
Save mode only requires setting the PSM bit.
When the WBPSM bit is set, a switch from Ac-
tive mode to Power Save, Idle, or Halt mode is
performed by setting the PSM, IDLE or HALT
bit, respectively, and then executing a WAIT
instruction. Also, if the DMC or DHC bits are
set, the high-frequency oscillator and PLL
may be disabled only after a WAIT instruction
is executed and the Power Save, Idle, or Halt
mode is entered.
0
– Mode transitions may occur immediately.
1 – Mode transitions are delayed until the
next WAIT instruction is executed.
DMC The Disable Main Clock bit may be used to
disable the high-frequency oscillator in Power
Save and Idle modes. In Active mode, the
high-frequency oscillator is enabled without
regard to the DMC value. In Halt mode, the
high-frequency oscillator is disabled without
regard to the DMC value. The DMC bit is
cleared by hardware when a hardware wake-
up event is detected.
0
– High-frequency oscillator is only disabled
in Halt mode or when disabled by the
HCC mechanism.
1 – High-frequency oscillator is also disabled
in Power Save and Idle modes.
DHC The Disable High-Frequency (PLL) Clock bit
and the CRCTRL.PLLPWD bit may be used to
disable the PLL in Power Save and Idle
modes. When the DHC bit is clear (and PLL-
PWD = 0), the PLL is enabled in these modes.
If the DHC bit is set, the PLL is disabled in
Power Save and Idle mode. In Active mode
with the CRCTRL.PLLPWD bit set, the PLL is
enabled without regard to the DHC value. In
Halt mode, the PLL is disabled without regard
to the DMC value. The DHC bit is cleared by
hardware when a hardware wake-up event is
detected.
0
– PLL is disabled only by entering Halt
mode or setting the CRCTRL.PLLPWD
bit.
1 – PLL is also disabled in Power Save or Idle
mode.
HCCM The Hardware Clock Control for Main Clock
bit may be used in Power Save and Idle
modes to disable the high-frequency oscillator
conditionally, depending on whether the Blue-
tooth LLC is in Sleep mode. The DMC bit must
be clear for this mechanism to operate. The
HCCM bit is automatically cleared when the
device enters Active mode.
0
– High-frequency oscillator is disabled in
Power Save or Idle mode only if the DMC
bit is set.
1 – High-frequency oscillator is also disabled
if the Bluetooth LLC is idle.
HCCH The Hardware Clock Control for High-Fre-
quency (PLL) bit may be used in Power Save
and Idle modes to disable the PLL condition-
ally, depending on whether the Bluetooth LLC
is in Sleep mode. The DHC bit and the CRC-
TRL.PLLPWD bit must be clear for this mech-
anism to operate. The HCCH bit is
automatically cleared when the device enters
Active mode.
0
– PLL is disabled in Power Save or Idle
mode only if the DMC bit or the CRC-
TRL.PLLPWD bit is set.
1 – PLL is also disabled if the Bluetooth LLC
is idle.