Motorola DSP96002 - Manual (Page 105)

MOTOROLA DSP96002 USER’S MANUAL 7 - 19
7.4.8.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1
The Host Transmit Interrupt Enable (HTIE) bit is used to enable the Host Transmit Data interrupt when the
Host Transmit Data Empty (HTDE) status bit in the Host Status Register (HSR) is set. When HTIE is
cleared, HTDE interrupts are disabled. When HTIE is set, the Host Transmit Data interrupt request will occur
if HTDE is set. HTIE is cleared by HW/SW reset.
7.4.8.3 HCR Host Command Interrupt Enable (HCIE) Bit 2
The Host Command Interrupt Enable (HCIE) bit is used to enable Host Command vectored DSP96002 in-
terrupts when the Host Command Pending (HCP) status bit in the Host Status Register (HSR) is set. When
HCIE is cleared, HCP interrupts are disabled. When HCIE is set, the Host Command interrupt request will
occur if HCP is set. The starting address of this interrupt is determined by the Host Vector (HV). HCIE is
cleared by HW/SW reset.
7.4.8.4 HCR Host Flag 2 (HF2) Bit 3
The Host Flag 2 (HF2) bit is used as a general purpose flag for DSP96002 to host processor communica-
tion. HF2 may be set or cleared by the DSP96002. HF2 Status can be read in the ICS register by the host
processor. HF2 is cleared by HW/SW reset.
7.4.8.5 HCR Host Flag 3 (HF3) Bit 4
The Host Flag 3 (HF3) bit is used as a general purpose flag for DSP96002 to host processor communica-
tion. HF3 may be set or cleared by the DSP96002. HF3 Status can be read in the ICS register by the host
processor. HF3 is cleared by HW/SW reset.
HI Interrupt Sources (96002 side)
INTERRUPT SOURCE STATUS MASK Exception Starting Address
Port A Port B
Receive Data Full HRDF HRIE $00000020 $00000030
Transmit Data Empty HTDE HTIE $00000022 $00000032
X Memory Read HXRP HXRE $00000024 $00000034
Y Memory Read HYRP HYRE $00000026 $00000036
P Memory Read HPRP HPRE $00000028 $00000038
X Memory Write HXWP HXWE $0000002A $0000003A
Y Memory Write HYWP HYWE $0000002C $0000003C
P Memory Write HPWP HPWE $0000002E $0000003E
Host Command HCP HCIE 2*HV ($00000000-$000001FE)
Host Processor
—
H
–
R Structure
—
H
–
R SOURCE STATUS MASK
Receive Data Full RXDF RREQ
Transmit Data Empty TXDE TREQ
Transmitter Ready TRDY TYEQ
Figure 7-13. HI Interrupt Structure