Motorola DSP96002 User Manual

Page 139

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MOTOROLA

DSP96002 USER’S MANUAL

7 - 53

X DATA Memory Space

$FFFFFFFF IPR - Interrupt Priority Register

$FFFFFFFE BCRA - Port A Bus Control Register

$FFFFFFFD BCRB - Port B Bus Control Register

$FFFFFFFC PSR - Port Select Register

: RESERVED :

$FFFFFFF0 Reserved for OnCE Operation (OGDBR)

$FFFFFFEF HTXA/HRXA - HOSTA HTX/HRX Register

$FFFFFFEE HTXCA - HOSTA HTX Reg. and HMRC Clear

$FFFFFFED HSRA - HOSTA Status Register

$FFFFFFEC HCRA - HOSTA Control Register

: RESERVED :

$FFFFFFE7 HTXB/HRXB - HOSTB HTX/HRX Register

$FFFFFFE6 HTXCB - HOSTB HTX Reg. and HMRC Clear

$FFFFFFE5 HSRB - HOSTB Status Register

$FFFFFFE4 HCRB - HOSTB Control Register

: RESERVED :

$FFFFFFE0 RESERVED

$FFFFFFDF DSM0 -DMA CH0 Source Modifier Register

$FFFFFFDE DSR0 -DMA CH0 Source Address Register

$FFFFFFDD DSN0 -DMA CH0 Source Offset Register

$FFFFFFDC DCO0 -DMA CH0 Counter Register

$FFFFFFDB DDM0 -DMA CH0 Destination Modifier Register

$FFFFFFDA DDR0 -DMA CH0 Destination Address Register

$FFFFFFD9 DDN0 -DMA CH0 Destination Offset Register

$FFFFFFD8 DCS0 -DMA CH0 Control/Status Register

$FFFFFFD7 DSM1 -DMA CH1 Source Modifier Register

$FFFFFFD6 DSR1 -DMA CH1 Source Address Register

$FFFFFFD5 DSN1 -DMA CH1 Source Offset Register

$FFFFFFD4 DCO1 -DMA CH1 Counter Register

$FFFFFFD3 DDM1 -DMA CH1 Destination Modifier Register

$FFFFFFD2 DDR1 -DMA CH1 Destination Address Register

$FFFFFFD1 DDN1 -DMA CH1 Destination Offset Register

$FFFFFFD0 DCS1 -DMA CH1 Control/Status Register

$FFFFFFCF RESERVED

: RESERVED :

$FFFFFF80 RESERVED

Figure 7-27. Internal I/O Memory Map

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