Motorola DSP96002 - Manual (Page 776)

D-24 DSP96002 USER’S MANUAL MOTOROLA
Figure D-11. The Multiply Unit
in the barrel shifter and normalization unit, after which they are added in the add unit. The result is then
rounded to 32-bits for SEP results, and to 24 bits for SP results, as indicated by the instruction opcode. The
type of rounding implemented depends on the rounding mode bits in the MR register. The rounded result is
stored in the middle portion (mantissa) of the destination register.
The subtract unit is a high speed 32-bit adder/subtracter, used in all floating-point non-multiply operations
and in all fixed point operations delivering a 32-bit result. For floating point operations, 32-bit mantissas (1
integer bit and 31 fractional bits) are first "aligned" for floating point subtraction in the barrel shifter and nor-
malization unit, after which they are subtracted in the subtract unit. The result is then rounded to 32-bits for
SEP results, and to 24 bits for SP results, as indicated by the instruction opcode. The type of rounding im-
plemented depends on the rounding mode bits in the MR register. The rounded result is stored in the middle
portion (mantissa) of the destination register for floating point operations, and in the low portion for fixed-
point operations. This is shown in Figure D-15.
The barrel shifter/normalization unit is used for the alignment of the two operand mantissas, needed for ad-
dition of two floating point numbers. The barrel shifter is a 32-bit left-right multibit shifter, which is also used
in fixed point arithmetic and logic shifting operations with a 32-bit result. For the addition of two floating point
operands, the barrel shifter receives the exponent difference of the two operand exponents from the expo-
nent comparator and update unit, and uses this difference to align the mantissas for addition. For example,
if the biased exponent of the first floating point operand equals 10 and the biased exponent of the second
floating point operand equals 13, the mantissa of the first operand will be right shifted by three positions (3
bit shift).
The exponent comparator and update unit consists of an 11 bit subtracter, which compares the two expo-
nents of floating point operands, and delivers the difference to the barrel shifter for mantissa alignment. The
largest of the two exponents is delivered to the exponent update unit. The exponent update unit may update
Exponent Adder Multiplier Array Control
ES1 ES2 MS1 MS2
ED MD