Motorola DSP96002 User Manual
Page 754
D-2
DSP96002 USER’S MANUAL
MOTOROLA
are intended to provide some kind of retrospective diagnostic information concerning the origin
of the NaN. Since this information needs to remain available even after a large number of arith-
metic operations, QNaNs "propagate" unchanged through arithmetic operations and format
conversions. QNaNs can thus occur as operands of an arithmetic operation. If one or more
QNaN occur as operands, the result is a quiet NaN, and no floating point exception is signaled.
Hence the name "quiet" NaN. The standard specifies that at least one QNaN must be support-
ed.
Signaling NaNs (SNaNs):
Signaling NaNs are used only in systems with arithmetic-like en-
hancements that are not defined by the standard. As opposed to QNaNs, they are never gen-
erated by the DSP96002 arithmetic. They can, however, appear as operands in arithmetic op-
erations (as generated by other processors, for instance). In this case, they always signal the
"Invalid Operation" floating point exception. The returned result is a QNaN.
Floating point operands in the DSP96002 are either 32-bits long (Single Real), 64 bits long (Double Real)
or 96 bits long (Register operand). The operand size is either explicitly encoded in the instruction or implicitly
defined by the instruction operation. The following sections describe the details of each operand type.
D.1.2 DSP96002 Floating Point Storage Format in Memory
DP and SP are the only floating point formats for which the IEEE standard provides bit-level definitions.
Since the DSP96002 is designed for multiprocessing applications, where data in memory can be shared
among different processors, SP and DP are the only formats supported for memory storage of floating point
numbers.
SP numbers are represented by 32-bits in memory, and can be located in either X: or Y: data spaces. DP
numbers take up 64 bits in memory, and can thus only be stored in long (L:) memory space.
The basic formats (SP and DP) contain three fields in their binary representation, as shown in Figure D-1.
These fields are described as:
1.
Sign Bit (s): The sign bit denotes the sign of the number, in a signed magnitude notation. When
s=0, the number is positive. When s=1, the number is negative. Note that floating-point num-
bers do not use a two’s complement notation.
2.
Exponent Field (e): The exponent of SP and DP numbers is stored as a positive (biased) inte-
ger:
e = E + bias
where
E
is the actual exponent of the floating point number as explained in Appendix D.1.1.
e
is also used in conjunction with the fractional field f to encode non-numerical values (infinities
and NaNs).
For SP, the exponent consists of 8 bits (bits 23 through 30) , and the bias equals 127. The bi-
ased exponent
e
can thus take on integer values between 0 (denoted by
e
min
-1
) and 255 (de-
noted by
e
max
+1
) inclusive.
For DP, the exponent consists of 11 bits (bits 52 through 62) , and the bias equals 1023. Values
for the biased exponent e thus fall between 0 (
e
min
-1
) and 2047 (
e
max
+1
), inclusive. Table D-1
summarizes these values for SP and DP.
3.
Fraction (f): The fractional field consists of bits b
i
: