Motorola DSP96002 - Manual (Page 834)

52 MOTOROLA
7.3 Exception Priorities within an IPL
If more than one exception is pending when an instruction is executed, the interrupt with
the highest priority level is serviced first. Within a given interrupt priority level, a second
priority structure determines which interrupt is serviced when multiple interrupt requests
with the same IPL are pending.
Table 6 DSP96002 Exception Priorities within an IPL
Priority Exception Enabled by
highest Hardware RESET -
Illegal Instruction -
Stack Error -
(F)TRAPcc -
IRQA (External Interrupt) (IPR) IAL1-IAL0
IRQB (External Interrupt) (IPR) IBL1-IBL0
IRQC (External Interrupt) (IPR) ICL1-ICL0
Host A Command Interrupt (HCR) HCIE
Host A Receive Data Interrupt (HCR) HRIE
Host A Read X Memory Interrupt (HCR) HXRE
Host A Read Y Memory Interrupt (HCR) HYRE
Host A Read P Memory Interrupt (HCR) HPRE
Host A Write X Memory Interrupt (HCR) HXWE
Host A Write Y Memory Interrupt (HCR) HYWE
Host A Write P Memory Interrupt (HCR) HPWE
Host A Transmit Data Interrupt (HCR) HTIE
Host B Command Interrupt (HCR) HCIE
Host B Receive Data Interrupt (HCR) HRIE
Host B Read X Memory Interrupt (HCR) HXRE
Host B Read Y Memory Interrupt (HCR) HYRE
Host B Read P Memory Interrupt (HCR) HPRE
Host B Write X Memory Interrupt (HCR) HXWE
Host B Write Y Memory Interrupt (HCR) HYWE
Host B Write P Memory Interrupt (HCR) HPWE
Host B Transmit Data Interrupt (HCR) HTIE
DMA Channel 0 Interrupt (DCS0) DIE0
DMA Channel 1 Interrupt (DCS1) DIE1
Timer0 Interrupt (TCSR0) TIE0
lowest Timer1Interrupt (TCSR1) TIE1