Motorola DSP96002 - Manual (Page 27)

3 - 4 DSP96002 USER’S MANUAL MOTOROLA
3.2.6 Y Data Memory
The Y Data Memory may contain both data RAM and ROM. The Y Data RAM is a 32-bit wide internal mem-
ory and occupies the lowest 512 locations in Y Memory Space. The Y Data ROM is also a 32-bit wide in-
ternal memory and occupies 1024 locations in Y Memory Space. Addresses are received from the YAB
and data transfers occur on the YDB. The Y memory is dual-access memory in the sense that it may be
accessed twice during a cycle: once by the core and once by the DMA. Y memory may be expanded off
chip.
3.2.7 Program Control and System Stack
The Program Control logic performs instruction prefetch, instruction decoding and exception processing. A
32-bit program counter (PC) register can address 4,294,967,296 locations in Program Memory Space.
The System Stack is a separate internal RAM which stores the PC and the status register (SR) for subrou-
tine calls and long interrupts. The stack will also store the loop counter (LC) and the loop address register
(LA) in addition to the PC and SR registers for program looping. The System Stack is in Stack Memory
Space and its address is always inherent and implied by the current instruction. The stack RAM is 64-bits
wide and 15 locations "deep". When a subroutine call or long interrupt occurs, the contents of the PC and
SR registers are stored (pushed) on the "top" location in the System Stack. When a return from subroutine
occurs, the contents of the "top" location in the System Stack are copied (pulled) to the PC. When a return
from interrupt occurs, the contents of the "top" location in the System Stack are copied (pulled) to the PC
and SR.
An interrupt will cause the processor to enter the exception processing state. Upon entering this state, the
current instruction in decode will execute normally, unless it is the first word of a two-word instruction, in
which case it will be aborted, and re-fetched at the completion of exception processing. The next two fetch
addresses are supplied by the interrupt controller. During these fetches the PC is not updated.
If one of the words fetched by the interrupt controller is a jump to subroutine, a long interrupt routine is
formed, and a context switch is performed using the stack. If neither interrupt instruction word causes a
change of control flow, then the two interrupt instructions fetched constitute a fast interrupt routine. In this
case, the stack is not used, and interrupt service concludes with the execution of the instructions contained
within the two words. Fetching then resumes using the PC. The fast interrupt routine provides minimum
overhead exception processing. This mechanism is commonly used to move data between memory and
an I/O device.
For more details on the behavior of interrupts, see Section 8.
The system stack is also used to implement no-overhead hardware program loops. When a program loop
is initiated with the execution of a DO instruction, the following events occur:
• the current 32-bit loop counter (LC) and 32-bit loop address register (LA) are pushed onto the
system stack to allow nested loops.
• the LC and LA registers are initialized with values specified in the DO instruction.
• the address of the first instruction in the program loop and the current status register contents
are transferred onto the system stack.
• the loop flag bit in the status register is set.
The loop flag bit is set when a program loop is in progress and enables the end of loop detection (compar-
ison between the PC and LA registers, discussed below). The loop flag bit is pulled from the system stack
when a loop is terminated and indicates if the terminated loop was a nested loop.