Motorola DSP96002 - Manual (Page 84)

6 - 8 DSP96002 USER’S MANUAL MOTOROLA
field specifies the operands to be used by the adder/subtracter opcode. One of the Opcode fields must al-
ways be included in the source code.
The X Bus Data field specifies an optional data transfer over the X Bus and the addressing mode to be
used. The Y Bus Data field specifies an optional data transfer over the Y Bus and the addressing mode to
be used. The address space qualifiers X:, Y: and L: indicate which address space is being referenced.
The DSP96002 offers parallel processing of the Data ALU, Address Generation Unit and Program Control-
ler. For the instruction word above, the DSP96002 will perform the designated floating-point multiplier op-
eration (Data ALU), the designated floating-point adder/subtracter operation (Data ALU), the data transfers
specified with address register updates (Address Generation Unit), and will also decode the next instruction
and fetch an instruction from program memory (Program Controller) all in one instruction cycle. When an
instruction is more than one word in length, an additional instruction execution cycle is required.
Most instructions involving the Data ALU are register-based (all operands are in Data ALU registers) and
allow the programmer to keep each parallel processing unit busy. An instruction which is memory-oriented
(such as a bit manipulation instruction) or that causes a control flow change (such as a jump) prevents the
use of parallel processing resources during its execution.
6.4 INSTRUCTION EXECUTION
Instruction execution is pipelined to allow most instructions to execute at a rate of one instruction every
instruction cycle. However, certain instructions will require additional time to execute. These include in-
structions which are longer than one word, instructions which use an addressing mode that requires more
than one cycle, instructions which make use of the global data bus more than once, and instructions which
cause a control flow change. In the latter case a cycle is needed to clear the pipeline.
6.4.1 Instruction Processing
Pipelining allows the fetch-decode-execute operations of an instruction to occur during the fetch-decode-
execute operations of other instructions. While an instruction is executing, the next instruction to be exe-
cuted is decoded, and the instruction to follow the instruction being decoded is fetched from program mem-
ory. If an instruction is two words in length, the additional word will be fetched before the next instruction
is fetched. Figure 6-9 demonstrates pipelining; F1, D1 and E1 refer to the fetch, decode and execute op-
erations, respectively, of the first instruction. The third instruction contains an instruction extension word
and takes two cycles to execute.
Each instruction requires a minimum of 12 clock phases to be fetched, decoded, and executed. A new
instruction may be started after four phases. Two word instructions require a minimum of 16 phases to
execute and a new instruction may start after eight phases.
F1 F2 F3 F3e F4 F5 F6 . . .
D1 D2 D3 D3e D4 D5 . . .
E1 E2 E3 E3e E4 . . .
Instruction Cycle: 1 2 3 4 5 6 7 . . .
Figure 6-9. Instruction Pipelining