Document Outline

• Title Page
  • Contents
  • Figures
  • Tables
• Chapter1 Overview
  • 1.1 Manual Organization
  • 1.2 Manual Conventions
  • 1.3 DSP56300 Core Features
  • 1.4 DSP56300 Core Functional Blocks
    • 1.4.1 Data ALU
      • 1.4.1.1 Data ALU Registers
      • 1.4.1.2 Multiplier-Accumulator (MAC)
    • 1.4.2 Address Generation Unit (AGU)
    • 1.4.3 Program Control Unit (PCU)
    • 1.4.4 PLL and Clock Oscillator
    • 1.4.5 JTAG TAP and OnCE Module
    • 1.4.6 On-Chip Memory
  • 1.5 Internal Buses
  • 1.6 DMA
  • 1.7 Peripherals
    • 1.7.1 General-Purpose Input/Output (GPIO) signals
    • 1.7.2 Host Interface (HI32)
    • 1.7.3 Enhance Synchronous Serial Interface (ESSI)
    • 1.7.4 Serial Communications Interface (SCI)
    • 1.7.5 Triple Timer Module
  • 1.8 Related Documents and Web Sites
• Chapter2 Signals/Connections
  • 2.1 Power
  • 2.2 Ground
  • 2.3 Clock
  • 2.4 PLL
  • 2.5 External Memory Expansion Port (Port A)
    • 2.5.1 External Address Bus
    • 2.5.2 External Data Bus
    • 2.5.3 External Bus Control
  • 2.6 Interrupt and Mode Control
  • 2.7 Host Interface (HI32)
  • 2.8 Enhanced Synchronous Serial Interface 0
  • 2.9 Enhanced Synchronous Serial Interface 1
  • 2.10 Serial Communications Interface (SCI)
  • 2.11 Timers
  • 2.12 JTAG and OnCE Interface
• Chapter3 Memory Configuration
  • 3.1 Program Memory Space
    • 3.1.1 Internal Program Memory
    • 3.1.2 Memory Switch Modes—Program Memory
    • 3.1.3 Instruction Cache
    • 3.1.4 Program Bootstrap ROM
  • 3.2 X Data Memory Space
    • 3.2.1 Internal X Data Memory
    • 3.2.2 Memory Switch Modes—X Data Memory
    • 3.2.3 Internal I/O Space—X Data Memory
  • 3.3 Y Data Memory Space
    • 3.3.1 Internal Y Data Memory
    • 3.3.2 Memory Switch Modes—Y Data Memory
    • 3.3.3 External I/O Space—Y Data Memory
  • 3.4 Dynamic Memory Configuration Switching
  • 3.5 Sixteen-Bit Compatibility Mode Configuration
  • 3.6 Internal Memory Configuration Summary
  • 3.7 Memory Maps
• Chapter4 Core Configuration
  • 4.1 Operating Modes
  • 4.2 Bootstrap Program
  • 4.3 Central Processor Unit (CPU) Registers
    • 4.3.1 Status Register (SR)
    • 4.3.2 Operating Mode Register (OMR)
  • 4.4 Configuring Interrupts
    • 4.4.1 Interrupt Priority Registers (IPRC and IPRP)
    • 4.4.2 Interrupt Table Memory Map
    • 4.4.3 Processing Interrupt Source Priorities Within an IPL
  • 4.5 PLL Control Register (PCTL)
  • 4.6 Bus Interface Unit (BIU) Registers
    • 4.6.1 Bus Control Register
    • 4.6.2 DRAM Control Register (DCR)
    • 4.6.3 Address Attribute Registers (AAR[0–3])
  • 4.7 DMA Control Registers 5–0 (DCR[5–0])
  • 4.8 Device Identification Register (IDR)
  • 4.9 JTAG Identification (ID) Register
  • 4.10 JTAG Boundary Scan Register (BSR)
• Chapter5 Programming the Peripherals
  • 5.1 Peripheral Initialization Steps
  • 5.2 Mapping the Control Registers
  • 5.3 Data Transfer Methods
    • 5.3.1 Polling
    • 5.3.2 Interrupts
    • 5.3.3 DMA
    • 5.3.4 Advantages and Disadvantages
  • 5.4 General-Purpose Input/Output (GPIO)
    • 5.4.1 Port B Signals and Registers
    • 5.4.2 Port C Signals and Registers
    • 5.4.3 Port D Signals and Registers
    • 5.4.4 Port E Signals and Registers
    • 5.4.5 Triple Timer Signals and Registers
• Chapter6 Host Interface (HI32)
  • 6.1 Features
  • 6.2 Overview
  • 6.3 Data Transfer Paths
    • 6.3.1 Host-to-DSP Data Path
    • 6.3.2 DSP-To-Host Data Path
  • 6.4 Reset States
  • 6.5 DSP-Side Operating Modes
    • 6.5.1 Terminate and Reset (DCTR[HM] = $0)
    • 6.5.2 PCI Mode (DCTR[HM] = $1)
    • 6.5.3 Universal (DCTR[HM] = $2) and Enhanced Universal (DCTR[HM] = $3) Bus Modes
    • 6.5.4 GPIO Mode (DCTR[HM] = $4)
    • 6.5.5 Self-Configuration Mode (DCTR[HM] = $5)
  • 6.6 Host Port Pins
  • 6.7 HI32 DSP-Side Programming Model
    • 6.7.1 DSP Control Register (DCTR)
    • 6.7.2 DSP PCI Control Register (DPCR)
    • 6.7.3 DSP PCI Master Control Register (DPMC)
    • 6.7.4 DSP PCI Address Register (DPAR)
    • 6.7.5 DSP Status Register (DSR)
    • 6.7.6 DSP PCI Status Register (DPSR)
    • 6.7.7 DSP Receive Data FIFO (DRXR)
    • 6.7.8 DSP Master Transmit Data Register (DTXM)
    • 6.7.9 DSPSlaveTransmitData Register (DTXS)
    • 6.7.10 DSP Host Port GPIO Direction Register (DIRH)
    • 6.7.11 DSP Host Port GPIO Data Register (DATH)
  • 6.8 Host-Side Programming Model
    • 6.8.1 HI32 Control Register (HCTR)
    • 6.8.2 Host Interface Status Register (HSTR)
    • 6.8.3 Host Command Vector Register (HCVR)
    • 6.8.4 Host Master Receive Data Register (HRXM)
    • 6.8.5 Host Slave Receive Data Register (HRXS)
    • 6.8.6 Host Transmit Data Register (HTXR)
      • 6.8.6.1 PCI Mode (DCTR[HM] = $1)
      • 6.8.6.2 Universal Bus mode (DCTR[HM] = $2 or $3)
    • 6.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)
    • 6.8.8 Status/Command Configuration Register (CSTR/CCMR)
    • 6.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID)
    • 6.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)
    • 6.8.11 Memory Space Base Address Configuration Register (CBMA)
    • 6.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)
    • 6.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP)
  • 6.9 HI32 Programming Model/Quick Reference
• Chapter7 Enhanced Synchronous Serial Interface (ESSI)
  • 7.1 ESSI Enhancements
  • 7.2 ESSI Data and Control Signals
    • 7.2.1 Serial Transmit Data Signal (STD)
    • 7.2.2 Serial Receive Data Signal (SRD)
    • 7.2.3 Serial Clock (SCK)
    • 7.2.4 Serial Control Signal (SC0)
    • 7.2.5 Serial Control Signal (SC1)
    • 7.2.6 Serial Control Signal (SC2)
  • 7.3 Operation
    • 7.3.1 ESSI After Reset
    • 7.3.2 Initialization
    • 7.3.3 Exceptions
  • 7.4 Operating Modes: Normal, Network, and On-Demand
    • 7.4.1 Normal/Network/On-Demand Mode Selection
    • 7.4.2 Synchronous/Asynchronous Operating Modes
    • 7.4.3 Frame Sync Selection
    • 7.4.4 Frame Sync Signal Format
    • 7.4.5 Frame Sync Length for Multiple Devices
    • 7.4.6 Word Length Frame Sync and Data Word Timing
    • 7.4.7 Frame Sync Polarity
    • 7.4.8 Byte Format (LSB/MSB) for the Transmitter
    • 7.4.9 Flags
  • 7.5 ESSI Programming Model
    • 7.5.1 ESSI Control Register A (CRA)
    • 7.5.2 ESSI Control Register B (CRB)
    • 7.5.3 ESSI Status Register (SSISR)
    • 7.5.4 ESSI Receive Shift Register
    • 7.5.5 ESSI Receive Data Register (RX)
    • 7.5.6 ESSI Transmit Shift Registers
    • 7.5.7 ESSI Transmit Data Registers (TX[2–0])
    • 7.5.8 ESSI Time Slot Register (TSR)
    • 7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)
    • 7.5.10 Receive Slot Mask Registers (RSMA, RSMB)
  • 7.6 GPIO Signals and Registers
    • 7.6.1 Port Control Registers (PCRC and PCRD)
    • 7.6.2 Port Direction Registers (PRRC and PRRD)
    • 7.6.3 Port Data Registers (PDRC and PDRD)
• Chapter8 Serial Communication Interface (SCI)
  • 8.1 Operating Modes
    • 8.1.1 Synchronous Mode
    • 8.1.2 Asynchronous Mode
    • 8.1.3 Multidrop Mode
      • 8.1.3.1 Transmitting Data and Address Characters
      • 8.1.3.2 Wired-OR Mode
      • 8.1.3.3 Idle Line Wakeup
      • 8.1.3.4 Address Mode Wakeup
  • 8.2 I/O Signals
    • 8.2.1 Receive Data (RXD)
    • 8.2.2 Transmit Data (TXD)
    • 8.2.3 SCI Serial Clock (SCLK)
  • 8.3 SCI After Reset
  • 8.4 SCI Initialization
    • 8.4.1 Preamble, Break, and Data Transmission Priority
    • 8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)
  • 8.5 Exceptions
  • 8.6 SCI Programming Model
    • 8.6.1 SCI Control Register (SCR)
    • 8.6.2 SCI Status Register (SSR)
    • 8.6.3 SCI Clock Control Register (SCCR)
    • 8.6.4 SCI Data Registers
      • 8.6.4.1 SCI Receive Register (SRX)
      • 8.6.4.2 SCI Transmit Register (STX)
  • 8.7 GPIO Signals and Registers
    • 8.7.1 Port E Control Register (PCRE)
    • 8.7.2 Port E Direction Register (PRRE)
    • 8.7.3 Port E Data Register (PDRE)
• Chapter9 Triple Timer Module
  • 9.1 Overview
    • 9.1.1 Triple Timer Module Block Diagram
    • 9.1.2 Individual Timer Block Diagram
  • 9.2 Operation
    • 9.2.1 Timer After Reset
    • 9.2.2 Timer Initialization
    • 9.2.3 Timer Exceptions
  • 9.3 Operating Modes
    • 9.3.1 Triple Timer Modes
      • 9.3.1.1 Timer GPIO (Mode 0)
      • 9.3.1.2 Timer Pulse (Mode 1)
      • 9.3.1.3 Timer Toggle (Mode 2)
      • 9.3.1.4 Timer Event Counter (Mode 3)
    • 9.3.2 Signal Measurement Modes
      • 9.3.2.1 Measurement Input Width (Mode 4)
      • 9.3.2.2 Measurement Input Period (Mode 5)
      • 9.3.2.3 Measurement Capture (Mode 6)
    • 9.3.3 Pulse Width Modulation (PWM, Mode 7)
    • 9.3.4 Watchdog Modes
      • 9.3.4.1 Watchdog Pulse (Mode 9)
      • 9.3.4.2 Watchdog Toggle (Mode 10)
      • 9.3.4.3 Reserved Modes
    • 9.3.5 Special Cases
    • 9.3.6 DMA Trigger
  • 9.4 Triple Timer Module Programming Model
    • 9.4.1 Prescaler Counter
    • 9.4.2 Timer Prescaler Load Register (TPLR)
    • 9.4.3 Timer Prescaler Count Register (TPCR)
    • 9.4.4 Timer Control/Status Register (TCSR)
    • 9.4.5 Timer Load Register (TLR)
    • 9.4.6 Timer Compare Register (TCPR)
    • 9.4.7 Timer Count Register (TCR)
• AppendixA Bootstrap Program
• ChapterB Programming Reference
  • B.1 Internal I/O Memory Map
  • B.2 Interrupt Sources and Priorities
  • B.3 Programming Sheets
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • H
  • I
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  • M
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  • O
  • P
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  • T
  • U
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  • W
  • X
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