Spectrum Brands Quad C6x VME64 - Manual (Page 23)

Spectrum Signal Processing Monaco Technical Reference
Processor Nodes
Part Number 500-00191 11
Revision 2.00
2.1. Processor Memory Configuration
Each ‘C6X DSP processor implements a 4 Gigabyte (full 32-bit) address space. This
address space is partitioned into internal memory space and external memory space.
External memory space is accessed through four memory select lines (CE0, CE1, CE2
and CE3).
2.1.1. Internal Memory
Internal memory space is further separated into three distinct regions:
•
internal program RAM (64Kbytes)
•
internal peripheral registers (2 Mbytes)
•
internal data RAM (64 Kbytes)
These three regions define memory space which is implemented in the DSP processor.
2.1.2. External Memory
External memory is segmented into 4 regions:
•
external memory interface CE0 (16 Mbytes)
•
external memory interface CE1 (4 Mbytes)
•
external memory interface CE2 (16 Mbytes)
•
external memory interface CE3 (16 Mbytes)
External memory (CE0, CE1, CE2 and CE3) consists of node local memory resources
which are accessed on the DSP Local Bus, but are external to the DSP processor. The
type of memory in each of the four CE regions is determined by settings in the internal
peripheral registers. All remaining memory in the 4 GB address space is reserved.
The internal peripheral registers for Monaco must be initialized to the values in the
following table upon reset for the board to operate.