Bus error interrupts – Spectrum Brands Quad C6x VME64 User Manual

Page 55

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Spectrum Signal Processing

Monaco Technical Reference

Interrupt Handling

Part Number 500-00191

43

Revision 2.00

SCV64 interrupts can be generated from the VMEbus (vectored) or internally by the
SCV64 (auto-vectored).

If the interrupt was caused by an external VMEbus interrupt the SCV64 initiates an
/IACK cycle on the VMEbus. The /IACK cycle is acknowledged by the interrupter
which puts its interrupt vector on the lower 8 data bits of the DSP’s data bus.

If the /KIPL lines were set due to an internal (auto-vectored) interrupt source the
SCV64 initiates an /IACK cycle on the VMEbus, but no value is place on the lower
8 data bits. The SCV64 terminates the cycle by asserting the /KAVEC signal.

The KAVEC bit (bit D3) in the

VSTATUS Register

can be read to determine which

type of interrupt was generated. After an IACK cycle is performed, it is set to “0” if the
value on the lower 8 bits is a valid interrupt vector; or to “1” if the value is not a valid
interrupt vector.

Auto-vectored interrupt sources can be cleared by accessing the SCV64 register set.
Refer to the SCV64 User Manual for more information.

8.7.

Bus Error Interrupts

Bus error interrupts (BUSERR_x) are generated whenever an access cycle from a node
or SCV64 DMA to the VME bus causes the SCV64 to generate a bus error.

This interrupt is routed only to INT4 of the ‘C6x responsible for causing the VME bus
error. On-board logic routes enabled SCV64 interrupts and the inter-processor VINTx
interrupts to INT4 as well.

Any node can also determine the status of the bus error interrupts by reading the

VSTATUS Register

at address 016D 8000h. A “1” in any of the following bit

positions of the register indicates which nodes have pending bus error interrupts.

Bit

Node Whose Access Caused the Bus Error

D4

Node A

D5

Node B

D6

Node C

D7

Node D

To clear the interrupt, the interrupted ‘C6x writes a “1” to the same bit in the

VSTATUS Register.

It must

also clear the appropriate bits in the SCV64 DCSR

register before the board can access the VME bus again.

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