Spectrum Brands Quad C6x VME64 - Manual (Page 35)

Spectrum Signal Processing Monaco Technical Reference
VME64 Bus Interface
Part Number 500-00191 23
Revision 2.00
4 VME64 Bus Interface
There are two separate VMEbus slave interfaces on the Monaco board. One is
implemented by the SCV64 and provides A32 and A24 VMEbus masters access to the
global shared bus. The second slave interface provides direct access to the Test Bus
Controller for debugging, and to the Host Port Interfaces (HPIs) of each ‘C6x. The HPI
provides support for code download, control, and data transfers from the VME64 bus.
4.1. VME Operation
The Monaco board requires a VME chassis (6U) with power supply. The board
automatically becomes VMEbus system controller (Syscon) if it resides at the top of the
VMEbus grant daisy chain. This capability is provided by the Tundra SCV64 interface
chip. Refer to the SCV64 User Manual for details.
The Monaco board has two VME backplane connectors: a 3 row P1 connector and a 5
row P2 connector.
The board may be installed in either a 5 row VME backplane or a 3 row backplane. The
two additional rows on the VME P2 connector (Z and D) only serve to route serial port
signals from DSP processor nodes A, B, C and D to the VME backplane, if the board is
configured for that option.
Note: If the Monaco board is installed in a 3 row VME chassis, serial port
routing will be restricted to the PEM and PMC sites only.
4.2. SCV64 Primary Slave A32/A24 Interface
The primary interface to the VME64 bus is based on Tundra Semiconductor
Corporation’s SCV64 VME64 Interface chip. This chip enables the Monaco board to act
as a master or a slave on the VME64 bus, and also provides VME interrupt capabilities.
Transfer rates of 40 MBytes/sec are supported between the SCV64 and the Global
Shared Bus SRAM once the bus has been acquired. The SCV64 cannot be pre-empted
from the Global Shared Bus and it does not have a bus ownership timer.
A host on the VME64 bus can access both the lower half (1 Mbyte) of Global SRAM
and the Hurricane control registers on a Monaco board in either A24 or A32 addressing
modes as shown in the following memory map.