Spectrum Brands Quad C6x VME64 - Manual (Page 60)

Monaco Technical Reference Spectrum Signal Processing
Registers
48 Part Number 500-00191
Revision 2.00
on reset.
BUSERRA Status of the last bus cycle access made to the SCV64 by node A, including
SCV64 register and VME master accesses. Set to “1” if there was an error.
Cleared by writing “10h” to the VSTATUS register. All other interrupts are
cleared when the source of the interrupt is cleared. This interrupt is cleared
on reset.
KAVEC Status of the interrupt vector last received on the data bus. High if the
vector was not valid. During the IACK cycle, a non-vectored interrupt
source causes this bit to be set, denoting a non-valid vector value on the
bus. This bit is cleared on reset. The next SCV64 register, IACK, or
VMEOUT cycle updates KAVEC. This signal is active high.
/KIPL2..0
The interrupt level of pending interrupts in the SCV64. These signals are
active low. For example, a value of 0x0 indicates that interrupt level 7 is
pending.