PC Concepts SHG2 DP - Manual (Page 24)

Processor and Chipset Intel® SHG2 DP Server Board Technical Product Specification
Intel Order Number C11343-001 Revision 1.0 12
• Four port USB interface
•
PCI-compatible timer/counter and DMA controllers
• APIC and legacy 8259 interrupt controller
•
Power management
• General purpose I/O
The following are descriptions of how each supported feature is implemented in SHG2.
2.4.1 PCI Interface
The CSB5 fully implements a 32-bit PCI master/slave interface, in accordance with the PCI
Local Bus Specification, Revision 2.2.
On the SHG2 baseboard, the PCI interface operates at
33 MHz, using the 5V-signaling environment.
2.4.2 PCI Bus Master IDE Interface
The CSB5 acts as a PCI-based fast IDE controller that supports programmed I/O transfers and
bus master IDE transfers. The CSB5 supports two fast ATA-100 IDE channels, supporting two
drives per channel. Two IDE connectors, primary and secondary, featuring 40 pins each (2 x
20), are provided on the baseboard.
The SHG2 ATA interface supports Ultra DMA 33/66/100 synchronous DMA mode transfers.
2.4.3 USB Interface
The CSB5 contains a USB controller and USB hub. The USB controller moves data between
main memory and the four USB connectors provided.
The SHG2 baseboard provides three external USB connector interfaces on the rear I/O panel.
All ports function identically and support the same bandwidth. The external connector is defined
by the USB Specification, Revision 1.1. The SHG2 baseboard also provides a proprietary 10-
pin internal USB header, as the fourth USB port routable to an external location such as a front
panel (see the Section 8, Connections, for interface specifics on all connectors).
2.4.4 BIOS Flash
The SHG2 baseboard incorporates a Fujitsu* 29LV800TA-90PFTN flash memory component.
The 29LV800TA-90PFTN is a high-performance 8-Mbit memory organized as 1 MB of 8 bits
each.
There are 16 64-KB blocks within this device.
The 8-bit flash memory provides 1024K x 8 of BIOS and non-volatile storage space. The flash
device is directly addressed as 20-bit XBUS memory.
2.4.5 Compatibility Interrupt Control
The CSB5 provides the functionality of two legacy 8259 programmable interrupt controller (PIC)
devices, for ISA-compatible interrupt handling.