PC Concepts SHG2 DP - Manual (Page 41)

Intel® SHG2 DP Server Board Technical Product Specification Server Management
Revision 1.0 Intel Order Number C11343-001 29
5. Server Management
The SHG2 server management features are implemented using the Sahalee BMC chip. The
Sahalee BMC is an ASIC packaged in a 156-pin BGA that contains a 32-bit reduced instruction
set computing (RISC) processor core and associated peripherals. Figure 7 illustrates the SHG2
server management architecture. A description of the hardware architecture follows the
diagram.
BASEBOARD
PROCESSOR SOCKETS
SMS #1
I/F
System LPC Bus
5V
12V
3.3V
-12V
Pow
e
r But
to
n
F
ro
n
t P
a
nel
N
M
I S
w
it
c
h
IERR (2)
Thermal Trip (2)
- Chassis ID
- Baseboard ID
- Power State
NMI
Chip set NMIs
Chip set SMI
CPU Voltage (2)
INTELLIGENT PLATFORM MANAGEMENT BUS (IPMB)
R
e
s
e
t Bu
tto
n
C
h
a
s
s
is
In
tr
u
s
io
n
P
o
w
e
r C
o
nn
ec
to
r
To Power
Distribution
Board
Baseboard
Temp 1
Pr
iv
ate
M
ana
ge
m
ent
Bu
s
s
e
s
RAM CODE
(updateable)
SMI
Platform
Management
Interrupt
Routing
Non-volatile, read-write storage
SENSOR
DATA
RECORDS
SYSTEM
EVENT
LOG
FRU INFO
& CONFIG
DEFAULTS
SMM-
BIOS
I/F
CO
M 2
CO
M
M
MUX
BBD COM2
CPU 'Core' Temp (2)
EMP
DIMM SPD (6)
Sp
eak
er
Po
w
e
r LE
D
F
aul
t S
ta
tus
L
E
D
FANs (6)
Sl
e
ep Bu
tton
N
e
tw
o
rk
Ac
ti
v
it
y LED
s
PCI PME
BASEBOARD
MANAGEMENT
CONTROLLER
(BMC)
System I/F
PORTS
1.5V
3.3V Standby
LVDS-B Term. 1
LVDS-A Term. 2
LVDS-A Term. 1
LVDS-B Term. 2
D
ri
v
e A
c
ti
v
ity
/F
a
u
lt
L
E
D
Sy
s
te
m
Ide
n
ti
fy
Bu
tton
NIC #1
NIC #2
RI (Wake-on-Ring)
Chassis
Intrusion
IS
OL
LVDS-A Term. 3
LVDS-B Term. 3
Hot-swap
Backplane
Header
Hot-swap
Backplane
Header
Aux. IPMB
Connector
Chip Set
ICMB
Transceiver
Header
Front Panel Connectors
Logic 2.5V
spkr
SMS #2
I/F
ACPI
EC
S
y
s
tem
I
nde
nt
if
y
LE
D
Figure 7. SHG2 Sahalee BMC Block Diagram