PC Concepts SHG2 DP - Manual (Page 89)

Intel® SHG2 DP Server Board Technical Product Specification General Specifications
Revision 1.0 Intel Order Number C11343-001 77
2. Voltage regulation limits shall be maintained over the entire AC input range and any steady
state temperature and operating conditions specified.
3. Voltages shall be stable as determined by bode plot and transient response. The combined
error of peak overshoot, set point, regulation, and undershoot voltage shall be less than or
equal to +/-5% of the output voltage setting. The transient response measurements shall
be made with a load changing repetition rate of 50Hz to 5kHz. The load slew rate shall not
be greater than 0.2A/
µ
s.
Table 67. Transient Load Requirements
Output
∆∆∆∆
Step Load Size Load Slew Rate Capacitive
Load
+3.3V 25% of max load 0.5 A/
µ
sec 1,000
µ
F
+5V 30% of max load 0.5 A/
µ
sec 1,000
µ
F
12V1+12V2+12V3 65% of max load 0.5 A/
µ
sec 1,000
µ
F
+5VSB 25% of max load 0.5 A/
µ
sec 10
µ
F