Panasonic MN103001G/F01K - Manual (Page 148)

Bus Controller (BC)
8-34
An
Dn
WEn
RE
CSn
EA
MCLK
SYSCLK
BCS BCE BCS BCE
REN
EA
WEN
Write Read
:Undefined
Fig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
Fig. 8-13-3 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Separate Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
An
Dn
WEn
RE
CSn
EA
MCLK
SYSCLK
BCS=0 BCE BCE
REN
EA
WEN
BCS=0
Write Read
: Undefined