Panasonic MN103001G/F01K - Manual (Page 158)

Bus Controller (BC)
8-44
(a) Read Timing
(b) Write Timing
Fig. 8-13-15 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
An
WE0
RE
CS2
MCLK
SYSCLK
D7-0
DK
EA
REN
DW
BCE
Consumed internally
by the BC
“H”
EA
REN
BCE
DW
A[0]=0 A[0]=1
DK detection start DK detection start
Read low-order side Read high-order side
: Undefined
Consumed internally
by the BC
An
WE0
RE
CS2
MCLK
SYSCLK
D7-0
DK
EA
WEN
DW
BCE
“H”
EA
WEN
BCE
DW
A[0]=0 A[0]=1
DK detection start DK detection start
Write low-order side Write high-order side
: Undefined
Consumed internally
by the BC Consumed internally
by the BC