Panasonic MN103001G/F01K - Manual (Page 168)

Bus Controller (BC)
8-54
Fig. 8-13-25 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in
Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
When BCE for the low-order bits is completed at the rising edge of SYSCLK, the bus cycle for the high-order bits
begins at the same rising edge of SYSCLK.
(a) Read Timing
(b) Write Timing
A23* to 16
RE
AS
CSn
ADE
ADM15 to 0
ASA
RWSEL
MCLK
SYSCLK
BCS
WE0
“H”
BCE
BCS
BCE
ASN
ADE
ASA
ASN
EA
REN
EA
REN
Read low-order side Read high-order side
data in data in
A[0]=0 “0”( ) “L” A[0]=1
A[0]=0 A[0]=1
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0”( ) “L”
A23* to 16
RE
AS
CSn
ADE
ADM15 to 0
ASA
RWSEL
MCLK
SYSCLK
BCS
WE0
“H”
BCE
BCS
BCE
ASN
ADE
ASA
ASN
EA
WEN
EA
WEN
Write low-order side Write high-order side
A[0]=0 A[0]=1
A[0]=1 data out data out A[0]=0
“0”(“L”)
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0”(“L”)