Panasonic MN103001G/F01K - Manual (Page 177)

Bus Controller (BC)
8-63
■ Minimum value for the RAS Precharge interval
When consecutive DRAM accesses are performed, the RAS precharge interval is shortest when performing an
access of type (1) or (2) below while the PAGE bit is set to “0” in the DRAM control register:
(1) Word/half-word access while the bus width is set to 8 bits
(2) Word access while the bus width is set to 16 bits
Because the minimum value for the RAS precharge interval is:
RP + ASR
as shown in Fig. 8-14-2, set the parameters RP and ASR to values that will satisfy the DRAM requirements. Note
that the minimum value that can be set for both RP and ASR is 1.
Fig. 8-14-2 Case Where the RAS Precharge Interval is at Its Minimum
(Example Where RP = 1 and ASR = 1)
ASR
CAO
RASn
CAS
ASC
RSH
Lower byte read
or
lower byte write
An Column Column Row Row
MCLK
RP
ASR
CAO
ASC
RSH
RE
CAS CAS
Upper byte read
or
upper byte write
Dn
Dn
WEn
WEN WEN
During reading
During writing