Pca9665 – NXP Semiconductors PCA9665 User Manual
Page 14
PCA9665_2
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
14 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
7.3.2.4
The Time-out register, I2CTO (indirect address 04h)
I2CTO is an 8-bit read/write register. It is used to determine the maximum time that SCL is
allowed to be in a LOW logic state before the I
2
C-bus state machine is reset or the
PCA9665 initiates a forced action on the I
2
C-bus.
When the I
2
C-bus interface is operating, I2CTO is loaded in the time-out counter at every
LOW SCL transition.
The Time-out register can be used in the following cases:
•
When the bus controller, in the master mode, wants to send a START condition and
the SCL line is held LOW by some other device. Then the bus controller waits a time
period equivalent to the time-out value for the SCL to be released. In case it is not
released, the bus controller concludes that there is a bus error, loads 78h in the
I2CSTA register, generates an interrupt signal and releases the SCL and SDA lines.
After the microcontroller reads the status register, it needs to send a reset in order to
reset the bus controller.
•
In the master mode, the time-out feature starts every time the SCL goes LOW. If SCL
stays LOW for a time period equal to or greater than the time-out value, the bus
controller concludes there is a bus error and behaves in the manner described above.
When the I
2
C-bus interface is operating, I2CTO is loaded in the time-out counter at
every SCL transition. See
for more information.
•
In case of a forced access to the I
2
C-bus. (See more details in
7.3.2.5
The Parallel Software Reset register, I2CPRESET (indirect address 05h)
I2CPRESET is an 8-bit write-only register. Programming the I2CPRESET register allows
the user to reset the PCA9665 under software control. The software reset is achieved by
writing two consecutive bytes to this register. The first byte must be A5h while the second
byte must be 5Ah. The writes must be consecutive and the values must match A5h and
5Ah. If this sequence is not followed as described, the reset is aborted.
Table 21.
I2CTO - Time-out register (indirect register 04h) bit allocation
7
6
5
4
3
2
1
0
TE
TO6
TO5
TO4
TO3
TO2
TO1
TO0
Table 22.
I2CTO - Time-out register (indirect register 04h) bit description
Bit
Symbol
Description
7
TE
Time-out enable/disable
TE = 1: Time-out function enabled
TE = 0: Time-out function disabled
6:0
TO[6:0]
Time-out value. The time-out period = (I2CTO[6:0] + 1)
×
143.36
µ
s.
The time-out value may vary some, and is an approximate value.