NXP Semiconductors PCA9665 - Manual (Page 8)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 8 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
7.3.1 Direct registers
7.3.1.1 The Status register, I2CSTA (A1 = 0, A0 = 0)
I2CSTA is an 8-bit read-only register. The two least significant bits are always zero. The
six most significant bits contain the status code. There are 30 possible status codes.
When I2CSTA contains F8h, it indicates the idle state and therefore no serial interrupt is
requested. All other I2CSTA values correspond to defined states. When each of these
states is entered, a serial interrupt is requested (SI = 1 and INT asserted LOW).
Remark: Data in I2CSTA is valid only when a serial interrupt occurs (SI = 1 and INT
asserted LOW). Reading the register when SI = 0 and INT is HIGH may cause wrong
values to be read.
7.3.1.2 The Indirect Pointer register, INDPTR (A1 = 0, A0 = 0)
INDPTR is an 8-bit write-only register. It contains a pointer to a register in the indirect
address space (IP[2:0]). The value in the register will determine what indirect register will
be accessed when the INDIRECT register is read or written, as defined in
Table 4 .
7.3.1.3 The I 2 C-bus Data register, I2CDAT (A1 = 0, A0 = 1)
I2CDAT is an 8-bit read/write register. It contains a byte of serial data to be transmitted or
a byte which has just been received. In master mode, this includes the slave address that
the master wants to send out on the I
2 C-bus, with the most significant bit of the slave
address in the SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU
can read from and write to this 8-bit register while the PCA9665 is not in the process of
shifting a byte. This occurs when PCA9665 is in a defined state and the serial interrupt
flag is set. Data in I2CDAT remains stable as long as SI is set. Whenever the PCA9665
generates an interrupt, the I2CDAT register contains the data byte that was just
transferred on the I
2 C-bus.
Table 5. I2CSTA - Status register (A1 = 0, A0 = 0) bit allocation
7 6 5 4 3 2 1 0
ST5 ST4 ST3 ST2 ST1 ST0 0 0
Table 6. I2CSTA - Status register (A1 = 0, A0 = 0) bit description
Bit Symbol Description
7:2 ST[5:0] status code corresponding to the different I 2 C-bus states
1:0 - always at zero
Table 7. INDPTR - Indirect Register Pointer (A1 = 0, A0 = 0) bit allocation
7 6 5 4 3 2 1 0
- - - - - IP2 IP1 IP0
Table 8. INDPTR - Indirect Pointer register (A1 = 0, A0 = 0) bit description
Bit Symbol Description
7:3 - reserved; must be written with zeroes
2:0 IP2 to IP0 address of the indirect register