NXP Semiconductors PCA9665 - Manual (Page 60)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 60 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
8.9.5 Bus error
A bus error occurs when a START or STOP condition is present at an illegal position in the
format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data or an acknowledge bit.
The PCA9665 only reacts to a bus error when it is involved in a serial transfer either as a
master or an addressed slave. When a bus error is detected, PCA9665 releases the SDA
and SCL lines, sets the interrupt flag, and loads the status register with 00h. This status
code may be used to vector to a service routine which either attempts the aborted serial
transfer again or simply recovers from the error condition as shown in
Table 46
“Miscellaneous states” . The microcontroller must send an external hardware or software
reset signal to reset the PCA9665.
8.10 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset holds the PCA9665 in a reset
condition until V
DD
has reached V
POR
. At this point, the reset condition is released and the
PCA9665 goes to the power-up initialization phase where the following operations are
performed:
1. ENSIO bit is set to 1 to enable the internal oscillator.
2. Internal register initialization is performed.
3. ENSIO bit is set to 0 to disable the internal oscillator and go to the non-addressed low
power mode.
The complete power-up initialization phase takes 550
µ
s to be performed. During this
time, write to the PCA9665 through the parallel port is not permitted. However, the parallel
port can be read. This allows the device connected to the parallel port of the PCA9665 to
poll the I2CCON register and read the ENSIO state bit. When ENSIO bit is equal to 1, this
means that the power-up initialization is in progress. When ENSIO is set to 0, this means
that the power-up initialization is done and that the PCA9665 is initialized and ready to be
used.
Fig 17. Recovering from a bus obstruction caused by a LOW level on SDA
1 2 3 4 5 6 7 8 9
002aab030
STOP
condition
START
condition
STA flag
SDA line
SCL line