Texas Instruments TLV1562 - Manual (Page 12)

Operational Overview
6 SLAA040
3 Operational Overview
This chapter discusses the software and hardware interface for the TLV1562.
Plus the overall operational sequence of the A/D interface is described.
3.1 Reference Voltage Inputs
The voltage difference between the VREFP and VREFM terminals determines
the analog input range, i.e., the upper and lower limits of the analog inputs that
produce the full-scale (output data all 1s) and zero-scale (output data all 0s)
readings, respectively.
For design reasons, this high-speed sampling ADC does not have a ground-
referenced input voltage range. Hence, level shifting is required unless the
application allows the signal to be ac coupled. Level shifting could be done with
single-supply op amps.
The absolute voltage values applied to VREFP, VREFM, and the analog input
should not be greater than the AV
DD
supply minus 1 V, or lower than 0.8 V. Other
input restrictions apply so consult the TLV1562 data sheet for further information.
The digital output is full scale when the analog input is equal to or greater than
the voltage on VREFP, and is zero scale when the input signal is equal to or lower
than VREFM.
3.2 Input Data Bits
The ADC contains the two user-accessible registers, CR0 and CR1. All user
defined features such as conversion mode, data output format or sample size are
programmed in CR0 and CR1. The data acquisition process must be started by
writing to these two registers. After this initialization, the converter processes
data in the same configuration until these registers are overwritten.