Texas Instruments TLV1562 - Manual (Page 9)

The Board
3 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
2.3.1.2 Simplification of Software Requirements Through Modified Interface
Of all the TLV1562 modes of operation, only the mono interrupt driven mode uses
the RD signal to start the conversion. This requires a very flexible handling of the
read signal and therefore has to be performed by a general-purpose output
signal. If the application excludes using the RD signal to start the conversion
(using CSTART instead). The TLV1562 RD input signal can be generated with
an OR gate, whose inputs are driven by IOSTRB and R/W signals from the DSP
(see Figure 2).
Using these connections saves the programming steps of setting/resetting RD
with the XF signal. Another advantage is having XF available to control the
CSTART signal. This saves busy times on the address bus (in Figure 1, CSTART
was generated through A0/A1.) and simplifies the software code.
CAUTION:
The time t
EN(DATAOUT)
between the RD high-to-low transition
(generated by the DSP) and the arrival of valid ADC output
data on the data bus is related to the capacitive load of the
bus. In most cases, the ADC come out of the 3-state mode
and supplies the correct voltage levels onto the bus lines in
less than 50 ns. Thus, the minimum number of I/O-wait states
becomes two (for t
EN(DATAOUT)
≤
50 ns).
Address
Decoder
01
10
11
≥
1
1: x
Divider
INT
CSTART
CS
RD
WR
CLKIN
D(0–9) D(0–9)
CLOCKOUT
R/W
IOSTRB
A1
A0
INT
TLV1562 TMS320C54x
XF
≥
1 &
Figure 2. TLV1562 to ’C54x DSP Interface of the EVM,
Using RD or the CSTART Signal to Start Conversion
2.3.2 Recyclic Architecture
One specialty of this ADC is its recyclic architecture. Instead of limiting the device
power by the highest possible resolution at the fastest speed, this converter is
able to work at three maximum speeds for three resolutions. The highest
resolution runs at 2MSPS maximum throughput rate; 8-bit resolution
corresponds to 3MSPS, and 4-bit resolution to 7MSPS.