Texas Instruments TLV1562 - Manual (Page 15)

The Serial DAC/DSP System
9 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
4 The Serial DAC/DSP System
The software configures the buffered DSP serial port to the 16-bit master mode
so that the DSP generates the frame sync signal at BFSX and the data clock at
BCLKX serial port terminals. Table 4 shows the connections between the DSP
and the DAC TLC5618A.
Table 4. DSP/DAC Interconnection
FROM DSP TO DSP TO DAC
BFSX BFSR CS
BCLKX CLKR I/O CLK
BDX BDR DATA IN
The following statements describe the generation and application of the
configuration and control signals.
•
The DSP BCLKX output provides a 20-MHz data clock, which is a divide-by-2
of the DSP master clock.
•
The DSP BDX output supplies the 16-bit control and data move to the
TLC5618A at DATA IN.
•
The DSP BFSX frame synchronization signal, connected to CS, triggers the
start of a new frame of data.
After the falling edge of FSX, the next 16 data clocks transfer data into the DSP
DR terminal and out of the DX terminal. Since this DSP/DAC interface is
synchronous, the FSX signal is sent to the FSR terminal, and the CLKX is sent
to the CLKR terminal.