Texas Instruments MSP50C6xx - Manual (Page 139)

Hardware Loop Instructions
4-53 Assembly Language Instructions
high word of the result is stored in the PH register and is 0x3FFF. The low word
is stored in A0~ as 0x0001. If the two numbers are considered as Q15 fraction-
al numbers (all bits are to the right of the decimal point), then the result will be
a Q30 number. To translate a Q30 number back to a Q15 number, first left shift
the number (MOV A0,PH, SHL A0,A0), and then truncate the lower word (ig-
nore A0~). When fractional mode is set, the left shift is done automatically
(MOV A0,PH). Thus, the desired Q15 result is already in the PH register.
4.7 Hardware Loop Instructions
These instructions enhance both execution speed and code space
requirements for procedures that use short loop sequences. Because of
pipeline delays and the software overhead associated with counting,
comparing and branching, software controlled structures are very inefficient
for short loops. To ease this burden, two basic types of hardware assisted loop
structures are included in the MSP50P614/MSP50C614 processor. Hardware
loop instructions are summarized in Table 4–42.
Repeatable Instructions: Most instructions can be repeated N+2 times with
zero software overhead. Repeated instructions are functionally identical to
coding the same instruction N+2 times in sequence. Repeat loops require a
RPT instruction to set a count length, N. This immediately precedes the
instruction to be repeated. This next instruction is repeated N+2 times. The
RPT instruction is useful for clearing RAM locations, filtering, etc. If the
repeating instruction utilizes auto–increments/decrements to either Rx or AC
registers (i.e. *R2++ or ++A), then the repeated modification controls will be
permanent. If the repeatable instruction is a string instruction, then the string
register (STR) will be replaced by N. During the execution of a RPT instruction,
interrupts are queued. Queued interrupts are serviced after the RPT operation
completes according to their priority.
String Instructions: String loops are enabled by direct field decodes in
classes 1, 2b, 3 and 6b and have no counter overhead. These instructions
automatically load the counter using the contents of the STR. String instruction
loops are different because they assume the references made to data memory
and accumulators are long data strings, causing pointers to auto–increment.
Incrementing pointers does not affect the permanent value stored in Rx or APn
registers. For arithmetic string operations, carries from one word operation will
automatically be linked to the carry in of the next word operation. Additionally,
status equal to zero will be detected on the result as a long string. These
combinations provide efficient and convenient means to operate between lists
or stings or between a fixed location and a list or string. All string instructions
have a suffix, S. In this text, string instructions are written as nameS. During