Texas Instruments MSP50C6xx - Manual (Page 50)

Clock Control
2-26
In addition to being individually enabled, all interrupts must be GLOBALLY
enabled before any one can be serviced. Whenever interrupts are globally
disabled, the interrupt flag register may still receive updates on pending trigger
events. Those trigger events, however, are not serviced until the next INTE
instruction is encountered.
After an interrupt service branch, it is the responsibility of the programmer to
re-SET the global interrupt enable, using the INTE instruction.
2.8 Clock Control
2.8.1 Oscillator Options
The C6xx has two oscillator options available. Either option may be enabled
using the appropriate control bits in the clock speed control register
(ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3, Clock Speed Con-
trol Register.
The first oscillator option, called the resistor-trimmed oscillator (RTO), is useful
in low-cost applications where accuracy is less critical. This option utilizes a
single external resistor to reference and stabilize the frequency of an internal
oscillator. The oscillator is designed to run nominally at 32 kHz. It has a low V
DD
coefficient and a low temperature coefficient (refer to the data sheet). The
reference resistor is mounted externally across pins OSC
IN
and OSC
OUT
. The
RTO oscillator is insensitive to variations in the lead capacitance at these pins.
The required value of the reference resistor is 470 k
Ω
(1%).
The second oscillator option, CRO for crystal referenced, is a real time clock
utilizing a 32.768 kHz crystal. The crystal is mounted externally across pins
OSC
IN
and OSC
OUT
.
2.8.2 PLL Performance
A software controlled PLL multiplies the reference frequency (generated from
either RTO or CRO) by integer multiples. This higher frequency drives the
master clock which, in turn, drives the CPU clock. The master clock (MC)
drives the circuitry in the periphery sections of the C6xx. The CPU Clock drives
the core processor; its rate determines the overall processor speed. The multi-
plier in the PLL circuit, therefore, allows the master clock and the CPU clock
to be adjusted between their minimum and maximum values.
For either oscillator option, the reference frequency (32.768 kHz) is multiplied
by four before it is accessed by the PLL circuit. The base frequency for the PLL,