Xilinx LogiCore PCI v3.0 - Manual (Page 38)

38 www.xilinx.com PCI v3.0.151 Getting Started Guide
UG157 August 31, 2005
Chapter 3: Family Specific Considerations R
This option is used to introduce additional delay on a global clock net. It is important to
note that this additional delay is observable on the CLK output of the PCI interface, which
is supplied to the user application. Timing constraints for the user application must be
generated with this in mind.