Xilinx LogiCore PCI v3.0 - Manual (Page 39)

PCI v3.0.151 Getting Started Guide www.xilinx.com 39
UG157 August 31, 2005
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Chapter 4
Functional Simulation
This chapter describes how to simulate the ping64 example design with global clocks using
the supported functional simulation tools. For the PCI 32 interface, substitute ping32 for
ping64. If you are using a design with reference clocks, substitute with pcim_top_r and
ping_tb with ping_tb_r.
Supported functional simulation tools include
•
Cadence NC-Verilog v.5.0
•
Model Technology ModelSim v5.7b
Cadence NC-Verilog
Before attempting functional simulation, ensure that the NC-Verilog environment is
properly configured.
1. To start, move into the functional simulation directory:
cd <Install Path>/verilog/example/func_sim
2. Edit the ping_tb.f file. This file lists command line arguments for NC-Verilog, and is
shown below:
../source/ping_tb.v
../source/stimulus.v
../source/busrecord.v
../source/dumb_arbiter.v
../source/dumb_targ32.v
../source/dumb_targ64.v
../source/pcim_top.v
../source/ping.v
../source/cfg_ping.v
../source/glbl.v
../../src/xpci/pci_lc_i.v
../../src/xpci/pcim_lc.v
+libext+.vmd+.v
-y <Xilinx Install Path>/verilog/src/unisims
-y <Xilinx Install Path>/verilog/src/simprims
3. Modify the library search path by changing <Xilinx Install Path> to match the
Xilinx installation directory, and then save the file.