Model technology modelsim, Verilog – Xilinx LogiCore PCI v3.0 User Manual
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PCI v3.0.151 Getting Started Guide
UG157 August 31, 2005
Chapter 4: Functional Simulation
R
Most of the files listed are related to the example design and its testbench. For other
testbenches, the following subset must be used for proper simulation of the PCI interface:
../source/glbl.v
../../src/xpci/pci_lc_i.v
../../src/xpci/pcim_lc.v
+libext+.vmd+.v
-y <Xilinx Install Path>/verilog/src/unisims
-y <Xilinx Install Path>/verilog/src/simprims
This list does not include any configuration file, user application, top level wrapper, or
testbench. These additional files are required for a meaningful simulation.
4.
To run the NC-Verilog simulation, type the following:
ncverilog -f ping_tb.f
NC-Verilog processes the simulation files and exits. The testbench prints status messages
to the console. After the simulation completes, view the ncverilog.log file to check for
errors.
The Simvision browser may be used to view the simulation results.
5.
If desired, start Simvision with the following command:
simvision
Model Technology ModelSim
Before attempting functional simulation, ensure that the ModelSim environment is
properly configured.
Verilog
1.
Navigate to the functional simulation directory:
cd <Install Path>/verilog/example/func_sim
2.
Edit the ping_tb.f file. This file lists command line arguments, and is shown below:
../source/ping_tb.v
../source/stimulus.v
../source/busrecord.v
../source/dumb_arbiter.v
../source/dumb_targ32.v
../source/dumb_targ64.v
../source/pcim_top.v
../source/ping.v
../source/cfg_ping.v
../source/glbl.v
../../src/xpci/pci_lc_i.v
../../src/xpci/pcim_lc.v
+libext+.vmd+.v
-y <Xilinx Install Path>/verilog/src/unisims
-y <Xilinx Install Path>/verilog/src/simprims