Xilinx LogiCore PCI v3.0 - Manual (Page 50)

50 www.xilinx.com PCI v3.0.151 Getting Started Guide
UG157 August 31, 2005
Chapter 5: Synthesizing a Design R
The final set of design files (the user application) is located in:
<Install Path>/vhdl/example/source
7. Navigate to the source directory, select the cfg_ping.vhd, pcim_top.vhd, and ping.vhd,
then click Add.
8. After adding the three final files (for a total of six source files), click OK to return to the
main project window.
9. In the Source Files list, view the list of newly added source files by double-clicking the
flowtest/vhdl
folder (if it is not already open). Drag to reorder the source files in
the hierarchical order shown in Figure 5-16 .
10. Click Change Result File to display the EDIF Result File dialog box; then move the to
following directory:
<Install Path>/vhdl/example/synthesis
11. Name the file pcim_top.edf and click OK to set the name of the result file and return
to the main project window.
Note : In practice, the directory for the EDIF result file does not need to be changed.
However, the sample processing scripts included with the example design assume that the
output EDIF files will be located in the synthesis directory.
Figure 5-16: Project Window with Source Files